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公开(公告)号：US09886395B2
公开(公告)日：2018-02-06
申请号：US14939052
申请日：2015-11-12
Applicant: International Business Machines Corporation
Inventor： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/00 , G06F12/121 , G06F12/0891
CPC classification number: G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.
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公开(公告)号：US20150378924A1
公开(公告)日：2015-12-31
申请号：US14314461
申请日：2014-06-25
Applicant: International Business Machines Corporation
Inventor： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.
Abstract translation: 一种基于商店压力来确定商店缓存条目的驱逐的工具。 该工具由一个或多个计算机处理器确定一个或多个新的存储高速缓存条目分配的计数值。 该工具由一个或多个计算机处理器确定是否超过新的存储高速缓存条目分配限制。 超过了确定新存储高速缓存条目分配限制的响应，该工具由一个或多个计算机处理器确定一个或多个现有存储高速缓存条目的分配值，该分配值指示一个或多个 现有存储缓存条目。 该工具通过一个或多个计算机处理器至少部分地基于一个或多个现有存储高速缓存条目的分配值来确定用于驱逐的至少一个分配类别。 该工具程序由一个或多个计算机处理器确定用于逐出一个或多个现有存储高速缓存条目的逐出请求设置。
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公开(公告)号：US09665486B2
公开(公告)日：2017-05-30
申请号：US15093088
申请日：2016-04-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
IPC: G06F3/00 , G06F9/46 , G06F12/0811 , G06F12/0846 , G06F12/0897 , G06F12/0817 , G06F12/0875
CPC classification number: G06F12/0811 , G06F12/0824 , G06F12/0846 , G06F12/0848 , G06F12/0875 , G06F12/0897 , G06F2212/283 , G06F2212/452 , G06F2212/622
Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.
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公开(公告)号：US09588893B2
公开(公告)日：2017-03-07
申请号：US14537131
申请日：2014-11-10
Applicant: International Business Machines Corporation
Inventor： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
CPC classification number: G06F12/0808 , G06F3/061 , G06F3/0638 , G06F3/0683 , G06F9/467 , G06F12/0811 , G06F12/084 , G06F12/0891 , G06F12/0897 , G06F2212/1016 , G06F2212/1024 , G06F2212/152 , G06F2212/6042 , G06F2212/608 , G06F2212/62
Abstract: A method to merge one or more non-transactional stores and one or more thread-specific transactional stores into one or more cache line templates in a store buffer in a store cache. The method receives a thread-specific non-transactional store address and a first data, maps the store address to a first cache line template, and merges the first data into the first cache line template, according to a store policy. The method further receives a thread-specific transactional store address and a second data, maps the thread-specific store address into a second cache line template, according to a store policy. The method further writes back a copy of a cache line template to a cache and invalidates a third cache line template, which frees the third cache line template from a store address mapping.
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公开(公告)号：US20160224467A1
公开(公告)日：2016-08-04
申请号：US15093088
申请日：2016-04-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0824 , G06F12/0846 , G06F12/0848 , G06F12/0875 , G06F12/0897 , G06F2212/283 , G06F2212/452 , G06F2212/622
Abstract: A hierarchical cache structure comprises at least one higher level cache comprising a unified cache array for data and instructions and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache and a data cache of a split second level cache are connected to a third level cache; and an instruction cache of a split first level cache is connected to the instruction cache of the split second level cache, and a data cache of the split first level cache is connected to the instruction cache and the data cache of the split second level cache.
Abstract translation: 分级缓存结构包括至少一个高级缓存，其包括用于数据和指令的统一高速缓存阵列和至少两个较低级别的高速缓存，每个高级缓存分别在指令高速缓存和数据高速缓存中。 分裂的第二级高速缓存的指令高速缓存和数据高速缓存连接到第三级高速缓存; 并且分离的第一级高速缓存的指令高速缓存连接到分离的第二级高速缓存的指令高速缓存，并且分离的第一级高速缓存的数据高速缓存连接到指令高速缓存和分离的第二级高速缓存的数据高速缓存。
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Patent Agency Ranking
公开(公告)号：US09378143B2
公开(公告)日：2016-06-28
申请号：US13788200
申请日：2013-03-07
Applicant: International Business Machines Corporation
Inventor： Khary J. Alexander , Christian Jacobi , Hans-Werner Tast , Patrick M. West
CPC classification number: G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
Abstract: Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
Abstract translation: 实施例涉及控制事务和非交易存储的可观察性。 一方面包括接收一个或多个存储指令。 一个或多个存储指令在活动事务中启动并且包括存储数据。 活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。 存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。 接收到有效事务终止的信号。 如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。
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公开(公告)号：US20160070654A1
公开(公告)日：2016-03-10
申请号：US14939052
申请日：2015-11-12
Applicant: International Business Machines Corporation
Inventor： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
CPC classification number: G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries.
Abstract translation: 一种基于商店压力来确定商店缓存条目的驱逐的工具。 该工具由一个或多个计算机处理器确定一个或多个新的存储高速缓存条目分配的计数值。 该工具确定是否超出新的存储缓存条目分配限制。 超过了确定新的存储高速缓存条目分配限制的响应，工具确定一个或多个现有存储高速缓存条目的分配值，该分配值指示一个或多个现有存储高速缓存条目中的每一个的分配类别。 该工具至少部分地基于一个或多个现有存储高速缓存条目的分配值，至少一个用于驱逐的分配类别。 该工具程序确定用于逐出一个或多个现有存储高速缓存条目的逐出请求设置。
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公开(公告)号：US20160062905A1
公开(公告)日：2016-03-03
申请号：US14935909
申请日：2015-11-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christian Habermann , Christian Jacobi , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/0897 , G06F12/0811 , G06F2212/1024 , G06F2212/604
Abstract: A hierarchical cache structure includes at least one real indexed higher level cache with a directory and a unified cache array for data and instructions, and at least two lower level caches, each split in an instruction cache and a data cache. An instruction cache of a split real indexed second level cache includes a directory and a corresponding cache array connected to the real indexed third level cache. A data cache of the split second level cache includes a directory connected to the third level cache. An instruction cache of a split virtually indexed first level cache is connected to the second level instruction cache. A cache array of a data cache of the first level cache is connected to the cache array of the second level instruction cache and to the cache array of the third level cache. A directory of the first level data cache is connected to the second level instruction cache directory and to the third level cache directory.
Abstract translation: 分级缓存结构包括至少一个具有目录的真实索引高级缓存和用于数据和指令的统一高速缓存阵列，以及至少两个低级高速缓存，每个低级缓存分别在指令高速缓存和数据高速缓存中。 分割的实际索引的二级高速缓存的指令高速缓存包括连接到实际索引的第三级高速缓存的目录和对应的高速缓存阵列。 分离的第二级高速缓存的数据高速缓存包括连接到第三级高速缓存的目录。 分割的虚拟索引的第一级高速缓存的指令高速缓存连接到第二级指令高速缓存。 第一级高速缓存的数据高速缓存的高速缓存阵列连接到第二级指令高速缓存的高速缓存阵列和第三级高速缓存的高速缓存阵列。 第一级数据高速缓存的目录连接到第二级指令高速缓存目录和第三级缓存目录。
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公开(公告)号：US20140281238A1
公开(公告)日：2014-09-18
申请号：US13843278
申请日：2013-03-15
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Christian Habermann , Christian Jacobi , Sascha Junghans , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0862 , G06F12/0897 , G06F2212/1024
Abstract: Systems and methods for providing data from a cache memory to requestors includes a number of cache memory levels arranged in a hierarchy. The method includes receiving a request for fetching data from the cache memory and determining one or more addresses in a cache memory level which is one level higher than a current cache memory level using one or more prediction algorithms. Further, the method includes pre-fetching the one or more addresses from the high cache memory level and determining if the data is available in the addresses. If data is available in the one or more addresses then data is fetched from the high cache level, else addresses of a next level which is higher than the high cache memory level are determined and pre-fetched. Furthermore, the method includes providing the fetched data to the requestor.
Abstract translation: 用于从缓存存储器向请求者提供数据的系统和方法包括以层级布置的多个高速缓存存储器级。 该方法包括从高速缓冲存储器接收数据取出请求，并使用一个或多个预测算法确定高于当前高速缓存存储器级别的一级的高速缓冲存储器级别中的一个或多个地址。 此外，该方法包括从高速缓冲存储器级别预取一个或多个地址，并确定该地址中的数据是否可用。 如果数据在一个或多个地址中可用，则从高高速缓存级别获取数据，否则确定并预取高于高缓存存储器级别的下一级的地址。 此外，该方法包括将提取的数据提供给请求者。
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公开(公告)号：US09658967B2
公开(公告)日：2017-05-23
申请号：US14314461
申请日：2014-06-25
Applicant: International Business Machines Corporation
Inventor： Uwe Brandt , Willm Hinrichs , Walter Lipponer , Martin Recktenwald , Hans-Werner Tast
IPC: G06F12/00 , G06F12/121 , G06F12/0891
CPC classification number: G06F12/121 , G06F12/0891 , G06F2212/69 , G06F2212/70
Abstract: A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries.
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