公开(公告)号：US10698079B2

公开(公告)日：2020-06-30

申请号：US15088478

申请日：2016-04-01

Applicant: Intel IP Corporation

Inventor： Igal Kushnir ,  Shmuel Ravid ,  Raanan Sover

IPC: G01S13/34 ,  G01S13/02 ,  G01S7/00 ,  H01Q3/36 ,  H01Q21/28 ,  H01Q21/29 ,  H01Q21/06

Abstract: Embodiments relate to systems methods and computer readable media to enable a wireless communication device are described. In one embodiment a wireless communication device is configured for phased array communications. The wireless communication device comprises radar circuitry to detect objects that scatter a transmit radiated signal from the wireless communication device. Control circuitry is used to adjust the transmit radiated power of the phased array communications based on information provided by the radar circuitry.

公开(公告)号：US11271477B2

公开(公告)日：2022-03-08

申请号：US16639782

申请日：2017-08-30

Applicant: Intel IP Corporation

Inventor： Eshel Gordon ,  Igal Kushnir ,  Assaf Ben-Bassat ,  Sarit Zur

IPC: H02M3/07 ,  H02M1/14 ,  H02M1/00

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

公开(公告)号：US10944409B2

公开(公告)日：2021-03-09

申请号：US16618420

申请日：2017-07-24

Applicant: INTEL IP CORPORATION

Inventor： Igal Kushnir

IPC: H03L7/093 ,  G04F10/00 ,  H03L7/091 ,  H03L7/099 ,  H04B1/04 ,  H04B1/16

Abstract: A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

公开(公告)号：US09923563B1

公开(公告)日：2018-03-20

申请号：US15389520

申请日：2016-12-23

Applicant: Intel IP Corporation

Inventor： Gil Horovitz ,  Elan Banin ,  Igal Kushnir ,  Aryeh Farber ,  Ran Krichman ,  Ofir Degani ,  Rotem Banin

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03K5/1565 ,  H03L7/0805 ,  H03L7/085 ,  H03L2207/10

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.