公开(公告)号：US3841926A

公开(公告)日：1974-10-15

申请号：US32039473

申请日：1973-01-02

Applicant: IBM

Inventor： GARNACHE R ,  SMITH W

IPC: G11C11/41 ,  H01L21/225 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/07 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L7/34

CPC classification number: H01L27/10805 ,  H01L21/2255 ,  H01L23/522 ,  H01L27/0733 ,  H01L2924/0002 ,  Y10S148/007 ,  Y10S148/02 ,  Y10S148/043 ,  Y10S148/102 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S257/927 ,  Y10S438/975 ,  H01L2924/00

Abstract: Integrated circuits of high density are fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as a polycrystalline silicon (polysilicon) field shield and metal interconnection lines, while also making provision for very precise alignment of subsequent layers to diffusions. A doped oxide containing a suitable dopant, such as arsenic in the case of a p-type silicon substrate, is deposited on the substrate. A pattern corresponding to desired diffusions is generated by normal photolithographic and etching techniques. A second, undoped oxide layer is thermally grown over the semiconductor substrate with dopant from the doped oxide simultaneously diffusing into areas of the substrate underlying the doped oxide. The undoped oxide serves to prevent autodoping. Thermally growing the undoped oxide layer converts a layer of the semiconductor surface not covered by doped oxide to the undoped oxide. Both oxide layers are then removed, leaving slight steps at the surface of the semiconductor substrate around the diffusion. The slight steps serve to allow very precise alignment of masks for subsequent process steps. Otherwise, the structure produced is very planar. An insulating layer, desirably a composite of silicon dioxide and silicon nitride in the case of a silicon substrate, is then formed on the substrate, followed by a layer of polycrystalline semiconductor, desirably doped to provide high conductivity. Openings are then etched in the polycrystalline semiconductor layer to allow formation of gate electrodes of FET''s, contact to the substrate, and contact of a subsequent interconnection metallization to diffusions in some of the circuits. A second insulating layer, such as silicon dioxide, is then grown on the polycrystalline semiconductor layer. Contact holes are then made to diffusions in the substrate, the substrate itself, and the polycrystalline silicon. The deposition and etching of an interconnection layer on the second insulating layer completes fabrication of the integrated circuit.

公开(公告)号：US3811076A

公开(公告)日：1974-05-14

申请号：US32039573

申请日：1973-01-02

Applicant: IBM

Inventor： SMITH W

IPC: G11C11/404 ,  H01L21/225 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L19/00

CPC classification number: H01L27/10829 ,  H01L21/2255 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S148/043 ,  H01L2924/00

Abstract: An integrated circuit structure of a field effect transistor (FET) serially connected to a capacitor has the capacitor formed by one of the current flow electrodes of the FET and by a polycrystalline silicon (polysilicon) field shield. The structure includes, in a semiconductor (e.g., silicon) substrate, of, e.g., p-type conductivity, two spaced regions of opposite conductivity type to that of the substrate, e.g., n-type. One of the spaced regions serves as a first plate of the capacitor and as a first current flow electrode of the FET. The other region serves as a second current flow electrode of the FET. A first insulating layer on the substrate has a polysilicon layer on it covering the two spaced regions and is directly and ohmically electrically connected to the substrate. The portion of the polysilicon layer over the spaced region serving as the first plate of the capacitor serves as the second plate of the capacitor. A second insulating layer covers the polysilicon layer and a second layer of conducting material, e.g., aluminum, is provided on the second insulating layer. The second conductive layer overlies the space between the two spaced regions and serves as a gate electrode for the FET. When employed as a memory circuit, the spaced region of opposite conductivity type to the substrate which does not serve as the first plate of the capacitor is desirably a diffused bit/sense line and the second conducting layer serves as a word line.

Abstract translation: 串联连接到电容器的场效应晶体管（FET）的集成电路结构具有由FET的电流流动电极之一和多晶硅（多晶硅）场屏蔽形成的电容器。 该结构在例如p型导电性的半导体（例如，硅）衬底中包括与衬底相反的导电类型的两个间隔区域，例如n型。 间隔开的区域之一用作电容器的第一板和FET的第一电流流动电极。 另一区域用作FET的第二电流流动电极。 衬底上的第一绝缘层在其上具有覆盖两个间隔区域的多晶硅层，并且直接和欧姆电连接到衬底。 在用作电容器的第一板的间隔区域上的多晶硅层的部分用作电容器的第二板。 第二绝缘层覆盖多晶硅层，并且在第二绝缘层上设置第二层导电材料，例如铝。 第二导电层覆盖两个间隔区域之间的空间，并且用作FET的栅电极。 当用作存储器电路时，不用作电容器的第一板的与衬底相反的导电类型的间隔区域期望地是扩散位/感测线，并且第二导电层用作字线。