公开(公告)号：US09716059B2

公开(公告)日：2017-07-25

申请号：US14840236

申请日：2015-08-31

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Osamu Futonagane

IPC分类号： H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L23/50

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors.

公开(公告)号：US09704795B2

公开(公告)日：2017-07-11

申请号：US14820963

申请日：2015-08-07

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Kota Noda

IPC分类号： H01L23/49 ,  H01L21/48 ,  H05K1/02 ,  H05K3/40 ,  H01L23/498 ,  H05K1/11

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0278 ,  H05K1/111 ,  H05K3/4015 ,  H05K2201/0376 ,  H05K2201/09827 ,  H01L2924/00

摘要： A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.

公开(公告)号：US09510450B2

公开(公告)日：2016-11-29

申请号：US14799887

申请日：2015-07-15

申请人： IBIDEN CO., LTD.

发明人： Toshiki Furutani ,  Yasushi Inagaki

IPC分类号： H05K1/09 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10 ,  H05K1/02 ,  H05K3/40

CPC分类号： H05K1/115 ,  H05K1/0271 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/0011 ,  H05K3/0017 ,  H05K3/061 ,  H05K3/103 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/094 ,  H05K2201/10674 ,  H05K2203/0384 ,  Y02P70/611

摘要： A printed wiring board includes a insulation layer, a first conductive layer embedded into first surface of the insulation layer and having surface exposed on the first surface of the insulation layer, a second conductive layer formed on second surface of the insulation layer and protruding from the second surface of the insulation layer, a via penetrating through the insulation layer and electrically connecting the first and second conductive layers, a solder-resist layer covering the first conductive layer and having an opening structure forming an exposed structure of the first conductive layer, and a metal layer formed on the exposed structure and protruding from the first surface of the insulation layer. The exposed structure of the first conductive layer includes pads positioned to mount an electronic component to the first conductive layer, and the metal layer has a solder layer formed on the metal layer and having a flat surface.

摘要翻译： 印刷电路板包括绝缘层，第一导电层，其嵌入绝缘层的第一表面并且具有暴露在绝缘层的第一表面上的表面;第二导电层，形成在绝缘层的第二表面上并从绝缘层突出 绝缘层的第二表面，穿过绝缘层并电连接第一和第二导电层的通孔，覆盖第一导电层并具有形成第一导电层的暴露结构的开口结构的阻焊层，以及 形成在暴露结构上并从绝缘层的第一表面突出的金属层。 第一导电层的暴露结构包括定位成将电子部件安装到第一导电层的焊盘，并且金属层具有形成在金属层上并具有平坦表面的焊料层。

公开(公告)号：US09060446B2

公开(公告)日：2015-06-16

申请号：US14279465

申请日：2014-05-16

申请人： Ibiden Co., Ltd.

发明人： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC分类号： H05K1/18 ,  H01G4/224 ,  H01G4/228 ,  H01G4/40 ,  H01L21/48 ,  H01L23/50 ,  H01L23/64 ,  H01L25/16 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46

CPC分类号： H05K1/115 ,  H01G2/06 ,  H01G4/12 ,  H01G4/224 ,  H01G4/228 ,  H01G4/248 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/181 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

摘要： A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

摘要翻译： 印刷电路板包括容纳层，容纳层中容纳的片状电容器器件，以及形成在容纳层上的堆积结构，使得堆积结构覆盖容纳层中的片状电容器器件。 积层结构具有安装导体结构，其被定位成将IC芯片装置安装在积层结构的表面上，使得IC芯片装置直接安装在芯片电容器装置上，每个芯片电容器装置具有电介质体， 所述积聚结构，形成在所述电介质体上且在所述电介质体的表面上延伸的第一电极，以及形成在所述电介质体上并在所述电介质体的表面上延伸的第二电极，并且所述电介质体介于所述第一电极 电极和第二电极。

公开(公告)号：US09263784B2

公开(公告)日：2016-02-16

申请号：US14702194

申请日：2015-05-01

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC分类号： H05K1/00 ,  H01P3/08 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC分类号： H01P3/081 ,  H05K1/0213 ,  H05K1/0228 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/10159

摘要： A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.

摘要翻译： 封装基板包括芯基板，第一堆积层和第二堆积层。 第一累积层包括最上层中间层，上内层中间层，包括第一焊盘和第二焊盘的最上层导电层，上第一导电层，上第二导电层，通过最上层中间层形成的通孔，并将上第一导电层 和第二焊盘，并且跳过通过最上层和上部内中间层形成的通孔，并连接最上面和上部第二导电层。 第二堆积层包括最下层的中间层，下层的内层，包含第三层的最下层的导电层，下部的第一导电层，下部的第二导电层，通过最下层的中间层形成的通孔，并连接下部第一导电层和第三层 并且跳过通过最下部和下部内部中间层形成的通孔并连接最下部和下部第二导电层。

公开(公告)号：US20130286615A1

公开(公告)日：2013-10-31

申请号：US13930617

申请日：2013-06-28

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC分类号： H05K1/18 ,  H05K3/46

CPC分类号： H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

摘要翻译： 一种印刷电路板的制造方法，其特征在于，在基板上形成开口部，将所述基板的开口部中的芯片电容器定位，使得所述芯片电容器容纳在所述基板的开口部，形成包含层间树脂 绝缘层和在基板的表面上的导电层和容纳在基板的开口部分中的芯片电容器，并且在构成堆积结构的凸起结构的表面上形成，以便安装IC芯片，使得开口中的芯片电容器 基板的一部分直接位于IC芯片的正下方。

公开(公告)号：US20130206466A1

公开(公告)日：2013-08-15

申请号：US13835505

申请日：2013-03-15

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Katsuyuki Sano

IPC分类号： H05K1/02 ,  H05K1/14

CPC分类号： H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multilayer printed wiring board includes a core substrate having a through-hole formed through the substrate, an interlayer insulation layer formed on the substrate and having a via conductor formed through the insulation layer, and a conductor layer formed on the insulation layer and connected to the via in the insulation layer. The substrate has multiplayer insulation structure, outer power layer formed on surface of the structure, outer ground layer formed on opposite surface of the structure, inner power layer formed inside the structure and inner ground layer formed inside the structure, each of the inner layers has tapered end having angle satisfying 2.8

摘要翻译： 多层印刷电路板包括具有通过基板形成的通孔的芯基板，形成在基板上并具有通过绝缘层形成的通孔导体的层间绝缘层，以及形成在绝缘层上的导体层， 绝缘层中的通孔。 所述基板具有多层绝缘结构，在所述结构的表面上形成的外层电力层，在所述结构的相对面上形成的外部地层，在所述结构内形成的内部电力层和在所述结构内形成的内部地层， 具有满足2.8

公开(公告)号：US09793241B2

公开(公告)日：2017-10-17

申请号：US15364364

申请日：2016-11-30

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/552

CPC分类号： H01L25/0655 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/185 ,  H05K3/4647 ,  H05K3/4682 ,  H01L2224/83005 ,  H01L2924/014 ,  H01L2924/00014

摘要： A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on a first surface of the lowermost resin insulating layer, a conductor post formed in the lowermost resin insulating layer such that the conductor post has an upper surface facing the first surface and a lower surface on the opposite side with respect to the upper surface, a semiconductor element embedded in the lowermost resin insulating layer such that the semiconductor element has an electrode facing the first surface and is positioned on a second surface side of the lowermost resin insulating layer, and via conductors formed in the lowermost resin insulating layer and including a first via conductor and a second via conductor such that the first via conductor is connecting the first conductor layer and the conductor post and that the second via conductor is connecting the first conductor layer and the electrode.

公开(公告)号：US09763319B2

公开(公告)日：2017-09-12

申请号：US14706269

申请日：2015-05-07

申请人： IBIDEN CO., LTD.

发明人： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC分类号： H05K7/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498

CPC分类号： H05K1/0243 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0949 ,  H05K2201/09518 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674 ,  H01L2924/00

摘要： A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

公开(公告)号：US09510447B2

公开(公告)日：2016-11-29

申请号：US14799860

申请日：2015-07-15

申请人： IBIDEN CO., LTD.

发明人： Toshiki Furutani ,  Yasushi Inagaki

IPC分类号： H05K1/09 ,  H05K1/11 ,  H05K3/10 ,  H05K3/40 ,  H05K3/00

CPC分类号： H05K1/09 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/103 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4038 ,  H05K2201/0341 ,  H05K2201/094 ,  H05K2203/0384 ,  Y02P70/611

摘要： A printed wiring board includes an insulation layer, a first conductive layer embedded into first surface of the insulation layer, a second conductive layer formed on second surface of the insulation layer, a via conductor penetrating through the insulation layer and electrically connecting the first and second layers, and a solder-resist layer covering the first layer and having an opening structure forming an exposed structure of the first layer. The exposed structure is formed to connect an electronic component to the first layer, and the first layer has a barrier-metal layer and a metal layer on the first layer such that the barrier-metal layer is on surface of the first layer and includes metal different from metal forming the metal layer and that the metal layer is on surface of the barrier-metal layer in the exposed structure and protruding from the first surface of the insulation layer.

摘要翻译： 印刷布线板包括绝缘层，嵌入绝缘层的第一表面中的第一导电层，形成在绝缘层的第二表面上的第二导电层，穿过绝缘层的通孔导体，并将第一和第二 层，以及覆盖第一层并具有形成第一层的暴露结构的开口结构的阻焊层。 形成暴露结构以将电子部件连接到第一层，并且第一层在第一层上具有阻挡金属层和金属层，使得阻挡金属层在第一层的表面上并且包括金属 与形成金属层的金属不同，并且金属层位于暴露结构中的阻挡金属层的表面上并且从绝缘层的第一表面突出。