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公开(公告)号：US09798661B2
公开(公告)日：2017-10-24
申请号：US14766911
申请日：2013-10-15
Applicant: Hitachi, Ltd.
Inventor： Yoshifumi Mimata , Yuko Matsui , Shintaro Kudo
IPC: G06F12/08 , G06F3/06 , G06F12/0802 , G06F12/0868
CPC classification number: G06F12/0802 , G06F3/06 , G06F3/0613 , G06F3/0659 , G06F3/0683 , G06F12/0868 , G06F2212/50
Abstract: A receiving controller which receives a read request out of first and second storage controllers transfers the read request to an associated controller which is associated with a read source storage area out of the first and second storage controllers when the receiving controller is not the associated controller. It is however the receiving controller that reads the read-target data from a read source storage device, writes the read-target data to a cache memory of the receiving controller, and transmits the read-target data written in the cache memory of the receiving controller to a host apparatus.
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公开(公告)号：US09535864B2
公开(公告)日：2017-01-03
申请号：US14632043
申请日：2015-02-26
Applicant: Hitachi, Ltd.
Inventor： Shintaro Kudo , Yusuke Nonaka
CPC classification number: G06F13/34 , G06F3/0611 , G06F3/0658 , G06F3/0659 , G06F3/067 , G06F13/1642
Abstract: The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.
Abstract translation: 本发明是一种集群存储系统，即使当从一个控制器的处理器发送对另一控制器的处理器的访问时，第二控制器的处理器能够对该访问的处理进行优先级处理，以便I / O处理是 也阻止了延迟。 利用本发明的存储系统，第一控制器的第一处理器通过区分由第二控制器的第二处理器处理的请求信息来区分待优先处理的请求信息， 第二处理器和处理不优先的请求信息，并且第二处理器通过区分要优先处理的请求信息和不优先处理的请求信息来获取请求信息。
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公开(公告)号：US09696922B2
公开(公告)日：2017-07-04
申请号：US14762039
申请日：2013-12-24
Applicant: Hitachi, Ltd.
Inventor： Naoya Okada , Yusuke Nonaka , Akihiko Araki , Shintaro Kudo , Makio Mizuno
IPC: G06F12/08 , G06F3/06 , G06F12/0875 , G06F12/06 , G06F12/0868 , G06F12/0893
CPC classification number: G06F3/0619 , G06F3/0647 , G06F3/0659 , G06F3/0688 , G06F3/0689 , G06F12/0638 , G06F12/08 , G06F12/0868 , G06F12/0875 , G06F12/0893 , G06F2212/222 , G06F2212/2228 , Y02D10/13
Abstract: A storage controller has a processor, a volatile first cache memory that is coupled to the processor and that temporarily stores data, a nonvolatile second cache memory that is coupled to a microprocessor and that temporarily stores data, and a battery that is configured to supply electrical power to at least the processor and the first cache memory when a power stoppage has occurred. The second cache memory includes a dirty data area for storing dirty data, which is data that is not stored in the storage device, and a remaining area other than the dirty data area. When a power stoppage has occurred, the processor stores as target data in the remaining area of the second cache memory either all or a part of the data stored in the first cache memory.
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Patent Agency Ranking
公开(公告)号：US20140281244A1
公开(公告)日：2014-09-18
申请号：US13701656
申请日：2012-11-14
Applicant: HITACHI, LTD.
Inventor： Shintaro Kudo , Yusuke Nonaka , Masanori Takada
CPC classification number: G06F3/0626 , G06F3/0659 , G06F3/067 , G06F12/0813 , G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/461 , G06F2212/463
Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.
Abstract translation: 本发明的示例性存储装置包括用于存储块I / O命令和文件I / O命令的数据的存储装置和包括块高速缓存区域和文件高速缓存区域的控制器。 控制器从文件I / O命令创建块I / O命令，并根据创建的块I / O命令访问存储设备。 在文件缓存区域缺少高速缓存接收到的第一文件I / O命令的第一数据的区域的情况下，控制器选择在文件高速缓存区域中新创建空闲区域的第一高速缓存方法之一，以缓存第一文件I / 文件高速缓存区域中的数据和缓存第一数据在块高速缓存区域中而不缓存文件高速缓存区域中的第一数据的第二高速缓存方法。
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公开(公告)号：US08799580B2
公开(公告)日：2014-08-05
申请号：US13643440
申请日：2012-10-11
Applicant: Hitachi, Ltd.
Inventor： Yuki Sakashita , Yusuke Nonaka , Shintaro Kudo
CPC classification number: G06F12/0862 , G06F3/061 , G06F3/065 , G06F3/0689 , G06F12/0802 , G06F12/0866 , G06F12/0888 , G06F12/126 , G06F2212/601
Abstract: To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or cache poisoning optimization execution processing according to an attribute of the access target volume on the basis of an access request. If the memory bus optimization execution processing is selected, CPU loads the target data into the CPU core after storing the target data in the main storage area, and if the cache poisoning optimization execution processing is selected, the CPU loads the target data into the CPU core after storing the target data in the temporary area of the CPU cache from the CPU memory, and the CPU core checks the target data which was loaded from the main storage area or the temporary area of the CPU cache.
Abstract translation: 提高CPU缓存命中率，改善I / O处理。 控制器是由CPU核心和CPU高速缓存组成的CPU，其中CPU基于访问请求，根据访问目标卷的属性来选择存储器总线优化执行处理或高速缓存中毒优化执行处理。 如果选择了存储器总线优化执行处理，则CPU将目标数据存储在主存储区域之后，将目标数据加载到CPU内核中，并且如果选择了高速缓存中毒优化执行处理，则CPU将目标数据加载到CPU 将目标数据从CPU存储器存储在CPU高速缓存的临时区域中，并且CPU核心检查从主存储区域或CPU高速缓存的临时区域加载的目标数据。
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公开(公告)号：US09946655B2
公开(公告)日：2018-04-17
申请号：US14765442
申请日：2013-10-09
Applicant: Hitachi, Ltd.
Inventor： Noboru Morishita , Shintaro Kudo , Yusuke Nonaka , Akira Yamamoto
IPC: G06F12/00 , G06F12/0868 , G06F13/10 , G06F3/06 , G06F11/14 , G06F12/0895
CPC classification number: G06F12/0868 , G06F3/0619 , G06F3/065 , G06F3/067 , G06F11/14 , G06F12/0895 , G06F13/10 , G06F2212/1016 , G06F2212/1041 , G06F2212/283 , G06F2212/313
Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.
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公开(公告)号：US10055272B2
公开(公告)日：2018-08-21
申请号：US15027830
申请日：2013-10-24
Applicant: HITACHI, LTD.
Inventor： Yusuke Nishihara , Yuko Matsui , Shintaro Kudo
CPC classification number: G06F11/079 , G06F3/06 , G06F3/0619 , G06F3/0634 , G06F3/0653 , G06F3/0689 , G06F11/0727 , G06F11/076 , G06F13/00 , G06F13/14 , G06F13/385
Abstract: Provided is a storage system which is connected to a host computer and whereby data is read and written. The storage system comprises: a storage device which stores the data; and a storage controller wherein an error is detected by one of a plurality of first sections which are sections upon a transfer path of the data with respect to the storage device in a full check mode, an error is detected by one of second sections which are fewer than the first sections in a regular mode, and a switch is made to the full check mode when the error is detected in the regular mode.
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公开(公告)号：US08984235B2
公开(公告)日：2015-03-17
申请号：US13701656
申请日：2012-11-14
Applicant: Hitachi, Ltd.
Inventor： Shintaro Kudo , Yusuke Nonaka , Masanori Takada
CPC classification number: G06F3/0626 , G06F3/0659 , G06F3/067 , G06F12/0813 , G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/461 , G06F2212/463
Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.
Abstract translation: 本发明的示例性存储装置包括用于存储块I / O命令和文件I / O命令的数据的存储装置和包括块高速缓存区域和文件高速缓存区域的控制器。 控制器从文件I / O命令创建块I / O命令，并根据创建的块I / O命令访问存储设备。 在文件缓存区域缺少高速缓存接收的第一文件I / O命令的第一数据的区域的情况下，控制器选择在文件高速缓存区域中新创建空闲区域的第一高速缓存方法之一，以缓存第一文件I / 文件高速缓存区域中的数据和缓存第一数据在块高速缓存区域中而不缓存文件高速缓存区域中的第一数据的第二高速缓存方法。
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