公开(公告)号：US20130094814A1

公开(公告)日：2013-04-18

申请号：US13704161

申请日：2011-09-05

Applicant: Hidetoshi Ishida ,  Hiroyoshi Maesoba ,  Tetsuji Tanaka

Inventor： Hidetoshi Ishida ,  Hiroyoshi Maesoba ,  Tetsuji Tanaka

IPC: G02B6/44

CPC classification number: G02B6/443 ,  G02B6/3887 ,  G02B6/3889

Abstract: A fiber-optic cable with a fitting capable of increasing connection strength between a fiber-optic cable and an optical connector, which includes a fiber-optic cable including a sheath and a tensile member, an inner ring mounted on a circumference of the sheath from a position where the tensile member is drawn out of the sheath through a slit to a front end of the sheath, and a fitting mounted on the circumference and including a first portion mounted from the position where the tensile member is drawn out of the sheath to a position of the sheath on a side opposite to the ring side, and a second portion mounted while covering a circumference of the ring, wherein the first portion connects with the sheath, and the end portion of the tensile member is sandwiched by the ring and the second portion.

Abstract translation: 一种具有能够增加光纤电缆和光学连接器之间的连接强度的配件的光纤电缆，其包括包括护套和拉伸构件的光纤电缆，安装在护套的圆周上的内环 其中所述拉伸构件通过狭缝从所述鞘被拉出到所述护套的前端的位置，以及安装在所述圆周上的配件，并且包括从所述拉伸构件从所述护套拉出的位置安装的第一部分， 所述护套位于与所述环侧相反的一侧的位置，以及第二部分，其安装成覆盖所述环的周边，其中所述第一部分与所述护套连接，并且所述拉伸构件的端部被所述环夹持， 第二部分。

公开(公告)号：US07656010B2

公开(公告)日：2010-02-02

申请号：US11898958

申请日：2007-09-18

Applicant: Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L23/58

CPC classification number: H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract translation: 半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。 钝化膜包括由氮化铝制成的第一子膜。

公开(公告)号：US20070176204A1

公开(公告)日：2007-08-02

申请号：US11699426

申请日：2007-01-30

Applicant: Tomohiro Murata ,  Hidetoshi Ishida

Inventor： Tomohiro Murata ,  Hidetoshi Ishida

IPC: H01L29/15 ,  H01L31/00 ,  H01L29/739

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/7843

Abstract: A field effect transistor includes a first semiconductor layer made of a first group III-V nitride; a second semiconductor layer formed on the first semiconductor layer, made of a second group III-V nitride and having a gate recess portion for exposing the first semiconductor layer therein; and a gate electrode formed on the first semiconductor layer in the gate recess portion. A product of stress applied by the second semiconductor layer to the first semiconductor layer and the thickness of the second semiconductor layer is 0.1 N/cm or less.

Abstract translation: 场效应晶体管包括由第一III-V族氮化物构成的第一半导体层; 形成在第一半导体层上的第二半导体层，由第二组III-V族氮化物制成，并具有用于在其中暴露第一半导体层的栅极凹部; 以及形成在所述栅极凹部中的所述第一半导体层上的栅电极。 由第二半导体层施加到第一半导体层的应力的产物和第二半导体层的厚度为0.1N / cm以下。

公开(公告)号：US07064359B2

公开(公告)日：2006-06-20

申请号：US10912567

申请日：2004-08-06

Applicant: Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/7787 ,  Y10S257/918

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0≦x≦1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0≦y≦1 and 0

Abstract translation: 开关半导体器件包括形成在包括碳化硅或蓝宝石的单晶衬底上的第一复合层，并且包括通式为N 1 Ga 1-x N，其中 0 <= x <= 1; 形成在第一化合物层上的第二化合物层，并且包含通式为Y 1，Y z，Ga 1-y z N，其中0 < = y <= 1，0

公开(公告)号：US06299361B1

公开(公告)日：2001-10-09

申请号：US09391387

申请日：1999-09-08

Applicant: Takashi Sasaki ,  Teruaki Nishida ,  Hidetoshi Ishida ,  Dai Yui ,  Kei Sunaga

Inventor： Takashi Sasaki ,  Teruaki Nishida ,  Hidetoshi Ishida ,  Dai Yui ,  Kei Sunaga

IPC: G02B638

CPC classification number: G02B6/3636 ,  G02B6/3652 ,  G02B6/368 ,  G02B6/3839

Abstract: The invention has an object to provide a method of making an optical fiber array in which bare fibers obtained by removing a coating of an optical fiber ribbon can be certainly arrayed on a V-groove substrate. A first feature of the invention is to use a positioning guide, and the positioning guide is provided with a recess portion having inclined wall surfaces, and its bottom portion is made to have a width equal to the whole width of the bare fibers in an arrayed state. By using this positioning guide, the optical fiber array can be made in a process as follows. In a state where bare fibers exposed by removing part of coating of tip portions of two fiber ribbons are alternately arranged, the positioning guide is raised from below. The bare fibers with irregular gaps are moved by the positioning guide and are arranged. In this state, the bare fibers are pressed by a fiber pressing member from above, and the V-groove substrate is raised, so that they are put on V grooves and are fixed by an adhesive.

Abstract translation: 本发明的目的是提供一种制造光纤阵列的方法，其中通过去除光纤带的涂层而获得的裸露纤维可以可靠地排列在V形槽衬底上。 本发明的第一个特征是使用定位引导件，并且定位引导件设置有具有倾斜壁面的凹部，并且其底部部分的宽度等于裸线纤维的整个宽度的排列 州。 通过使用该定位引导件，光纤阵列可以如下进行。 在通过移除两个光纤带的末端部分的涂层的一部分而露出的裸露纤维线交替布置的状态下，定位引导件从下方升高。 具有不规则间隙的裸露纤维通过定位引导件移动并被布置。 在这种状态下，裸纤维被纤维挤压件从上方挤压，V形槽衬底被升高，使它们放在V形槽上并用粘合剂固定。

公开(公告)号：US5339376A

公开(公告)日：1994-08-16

申请号：US942061

申请日：1992-09-09

Applicant: Toshiaki Kakii ,  Makoto Honjo ,  Hidetoshi Ishida ,  Hiroshi Katsura ,  Toru Yamanishi ,  Kazumichi Miyabe ,  Tadashi Haibara ,  Michito Matsumoto

Inventor： Toshiaki Kakii ,  Makoto Honjo ,  Hidetoshi Ishida ,  Hiroshi Katsura ,  Toru Yamanishi ,  Kazumichi Miyabe ,  Tadashi Haibara ,  Michito Matsumoto

IPC: G02B6/38 ,  G02B6/40

CPC classification number: G02B6/3865 ,  G02B6/3839 ,  G02B6/3873

Abstract: An optical connector for connecting optical fibers, comprises: a guide-groove substrate having grooves for positioning optical fibers and guide pins; an upper plate having groove portions each for covering the guide pins positioned in the guide grooves of the guide-groove substrate; elastic guide-pin pressing members each provided in the groove portions of the upper plate above portions where the guide pin grooves are in contact with the guide pins. In such a arrangement, it is preferable to form an oxide film on said V-grooves of the guide-groove substrate at least in the vicinity of contact points between the guide pins and the V-grooves. The optical connector further includes a resin molding portion for surrounding the substrate and the upper plate, the resin molding portion including a pair of opposite opened portions at a front and back surfaces thereof.

Abstract translation: 一种用于连接光纤的光连接器，包括：具有用于定位光纤和引导销的槽的导槽基板; 上板，其具有各自用于覆盖位于导向槽基板的引导槽中的引导销的槽部; 弹性导向销按压部件分别设置在所述上​​板的所述槽部中，所述槽部在所述导销槽与所述引导销接触的部分之上。 在这种布置中，优选至少在引导销和V形槽之间的接触点附近在导槽基板的所述V形槽上形成氧化膜。 光连接器还包括用于围绕基板和上板的树脂模制部分，树脂模制部分在其前表面和后表面上包括一对相对的开口部分。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

Applicant: Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H03K17/687

CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract translation: 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US07834380B2

公开(公告)日：2010-11-16

申请号：US11297386

申请日：2005-12-09

Applicant: Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

Inventor： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC: H01L29/66

CPC classification number: H01L21/28581 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

Abstract translation: 场效应晶体管包括由多个半导体膜的多层构成的第一半导体层和形成在第一半导体层上的第二半导体层。 源电极和漏电极形成在第二半导体层上以彼此间隔开。 在夹在源电极和漏极之间的第二半导体层的一部分中形成有在其内壁上具有绝缘膜的开口，以便在其中露出第一半导体层。 在开口部形成有与绝缘膜和开口底部的第一半导体层接触的栅电极。

公开(公告)号：US07595544B2

公开(公告)日：2009-09-29

申请号：US11382994

申请日：2006-05-12

Applicant: Masayuki Kuroda ,  Hidetoshi Ishida ,  Tetsuzo Ueda

Inventor： Masayuki Kuroda ,  Hidetoshi Ishida ,  Tetsuzo Ueda

IPC: H01L29/04

CPC classification number: H01L29/7787 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66462

Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrate in a crystal growth chamber; forming a low-temperature GaN buffer layer made of GaN as the III group nitride semiconductor, on a main surface of the sapphire substrate by a MOCVD method; and forming a GaN layer on the low-temperature GaN buffer layer by the MOCVD method. Here, a [11-20] axis of the GaN layer is perpendicular to the main surface of the sapphire substrate.

Abstract translation: 本发明的目的是提供一种能够实现由III族氮化物半导体构成的常关的场效应晶体管的半导体器件及其制造方法。 本发明包括：将蓝宝石衬底放置在晶体生长室中; 通过MOCVD方法在蓝宝石衬底的主表面上形成由GaN构成的III族氮化物半导体的低温GaN缓冲层; 并通过MOCVD法在低温GaN缓冲层上形成GaN层。 这里，GaN层的[11-20]轴垂直于蓝宝石衬底的主表面。

公开(公告)号：US07432531B2

公开(公告)日：2008-10-07

申请号：US11346266

申请日：2006-02-03

Applicant: Hidetoshi Ishida

Inventor： Hidetoshi Ishida

IPC: H01L31/0256 ,  H01L33/00

CPC classification number: H01L29/2003 ,  B82Y20/00 ,  G02B1/02 ,  H01L29/045 ,  H01L29/7787 ,  H01L33/16 ,  H01L33/20 ,  H01S5/2201 ,  H01S5/34333

Abstract: A semiconductor device, which can accurately control carrier density, includes: a single crystal substrate; a semiconductor layer which is made of hexagonal crystal with 6 mm symmetry and is formed on the single crystal substrate; a source electrode, a drain electrode and a gate electrode which are formed on the semiconductor layer, where the main surfaces of a GaN layer and an AlGaN layer constituting the semiconductor layer respectively include C-axis of the hexagonal crystal, and a length direction of a channel region in the semiconductor layer is parallel to the C-axis of the hexagonal crystal.

Abstract translation: 可以精确地控制载流子密度的半导体装置包括：单晶基板; 形成在单晶衬底上的由六边形晶体制成的对称6mm的半导体层; 形成在半导体层上的源电极，漏电极和栅电极，其中构成半导体层的GaN层和AlGaN层的主表面分别包括六方晶的C轴，长度方向 半导体层中的沟道区域平行于六方晶体的C轴。