METHOD OF MANUFACTURING TRANSLUCENT CERAMIC AND ORTHODONTIC MEMBER
    3.
    发明申请
    METHOD OF MANUFACTURING TRANSLUCENT CERAMIC AND ORTHODONTIC MEMBER 有权
    制造透明陶瓷和正交构件的方法

    公开(公告)号:US20090224442A1

    公开(公告)日:2009-09-10

    申请号:US12397516

    申请日:2009-03-04

    IPC分类号: B29C45/00

    摘要: A method of manufacturing a translucent ceramic is provided. The method comprises: mixing a raw powder and an organic binder and kneading them to obtain a compound, the raw powder containing an aluminum oxide powder and a magnesium oxide powder, and the organic binder containing a first organic component and a second organic component; molding the compound in a predetermined shape by an injection molding method to obtain a green body; debinding the organic binder contained in the green body to obtain a brown body; and sintering the brown body to obtain a sintered body of the translucent ceramic. When the softening point of the first organic component is defined as “T1” (° C.) and the softening point of the second organic component is defined as “T2” (° C.), the kneading step is carried out at a temperature in the range of T2 or higher but lower than T1 after the raw powder and the organic binder are preheated at a temperature in the range of T1 to T1+100(° C.). An orthodontic member is also provided.

    摘要翻译: 提供一种制造半透明陶瓷的方法。 该方法包括:将原料粉末和有机粘合剂混合并捏合以获得化合物,含有氧化铝粉末和氧化镁粉末的原料粉末和含有第一有机组分和第二有机组分的有机粘合剂; 通过注射成型法将化合物成型为预定形状以获得生坯; 脱泡生坯中含有的有机粘合剂以获得棕色体; 并烧结棕色体以获得半透明陶瓷的烧结体。 当第一有机组分的软化点定义为“T1”(℃),将第二有机组分的软化点定义为“T2”(℃)时,捏合步骤在温度 在T1至T1 + 100(℃)之间的温度下预热原料粉末和有机粘合剂之后,在T2以上且低于T1的范围内。 还提供了一个正畸的成员。

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20120114086A1

    公开(公告)日:2012-05-10

    申请号:US13277701

    申请日:2011-10-20

    申请人: Junichi HAYASHI

    发明人: Junichi HAYASHI

    IPC分类号: H04L7/00

    摘要: A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips.

    摘要翻译: 半导体器件包括:接口芯片,包括读定时控制电路,其响应于来自外部的命令信号和时钟信号输出与时钟信号同步的多个读控制信号,并且具有不同的 时间 核心芯片包括堆叠在接口芯片上的多个内部电路,并且每个都与读取的控制信号同步地执行由命令信号指示的操作。 根据本发明,不需要控制核心芯片的等待时间,从而将时钟信号提供给核心芯片。

    METHOD FOR MAUFACTURING DENTAL IMPLANT AND DENTAL IMPLANT
    5.
    发明申请
    METHOD FOR MAUFACTURING DENTAL IMPLANT AND DENTAL IMPLANT 有权
    用于制造牙科植入物和牙科植入物的方法

    公开(公告)号:US20090029321A1

    公开(公告)日:2009-01-29

    申请号:US12179636

    申请日:2008-07-25

    IPC分类号: A61C13/00

    摘要: A dental implant capable of reliably preventing elution of metal when the dental implant is applied within an oral cavity and capable of reliably preventing occurrence of mismatching (bumpy occlusion or the like) when the dental implant is fixed in place, and a method for manufacturing the dental implant are provided. In the method for manufacturing a dental implant including an abutment, the abutment is manufactured through the steps including a ceramic molded body production step for molding a ceramic molded body composition to obtain a ceramic molded body, an assembling step for assembling a titanium member and the ceramic molded body together to obtain an assembled body, a degreasing step for degreasing the assembled body so that the ceramic molded body is transformed into a ceramic degreased body, and a sintering step for sintering the assembled body to transform the ceramic degreased body into a ceramic member so that the ceramic member is firmly fixed to the titanium member.

    摘要翻译: 一种牙科植入物,其能够在将牙科植入物涂敷在口腔内时能够可靠地防止金属溶出,并且能够可靠地防止当牙植入物固定就位时发生不匹配(颠簸堵塞等),以及制造方法 提供牙科植入物。 在用于制造包括基台的牙科植入物的方法中,通过以下步骤制造基台,所述步骤包括陶瓷成形体制造步骤,用于模制陶瓷成型体组合物以获得陶瓷成型体,组装钛构件的组装步骤和 陶瓷成型体一起获得组装体,用于使组装体脱脂的脱脂步骤,使得陶瓷成型体转变为陶瓷脱脂体,以及烧结步骤,用于烧结组装体以将陶瓷脱脂体转变成陶瓷 使得陶瓷构件牢固地固定在钛构件上。

    SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE 审中-公开
    半导体存储器件,存储器控制器和包括这些的数据处理系统

    公开(公告)号:US20140078848A1

    公开(公告)日:2014-03-20

    申请号:US14085440

    申请日:2013-11-20

    IPC分类号: G11C11/406

    摘要: In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened.

    摘要翻译: 在一个实施例中,半导体存储器件接收刷新命令和地址信息,并将刷新控制信号和地址信息共同地提供给核心芯片。 每个核心芯片包括层地址比较电路,其确定地址信息是否分配自己的核心芯片,以及刷新控制电路,当地址信息分配自己的核心芯片时,刷新控制电路基于刷新控制信号刷新自己的存储器单元 。 通过这种布置,减少了刷新命令一次刷新的芯片的存储器容量,因此可以缩短刷新命令的最短发布间隔。

    DENTAL IMPLANT AND METHOD FOR MANUFACTURING DENTAL IMPLANT
    7.
    发明申请
    DENTAL IMPLANT AND METHOD FOR MANUFACTURING DENTAL IMPLANT 有权
    牙科植入物和制造牙科植入物的方法

    公开(公告)号:US20090029318A1

    公开(公告)日:2009-01-29

    申请号:US12179913

    申请日:2008-07-25

    IPC分类号: A61C8/00

    摘要: A dental implant capable of reliably preventing elution of metal when the dental implant is applied within an oral cavity and capable of reliably preventing occurrence of mismatching (bumpy occlusion or the like) when the dental implant is fixed in place, and a method for manufacturing the dental implant are provided. In the method for manufacturing a dental implant including an abutment, the abutment is manufactured through the steps including a titanium molded body production step for molding a titanium molded body composition to obtain a titanium molded body having one of male and female thread portions, a ceramic molded body production step for molding a ceramic molded body composition to obtain a ceramic molded body having the other thread portion which makes thread coupling with the one thread portion, an assembling step for assembling the titanium molded body and the ceramic molded body together so that the one thread portion makes thread coupling with the other thread portion, to obtain an assembled body, a degreasing step for degreasing the assembled body, and a sintering step for sintering the assembled body thus degreased.

    摘要翻译: 一种牙科植入物,其能够在将牙科植入物涂敷在口腔内时能够可靠地防止金属溶出,并且能够可靠地防止当牙植入物固定就位时发生不匹配(颠簸堵塞等),以及制造方法 提供牙科植入物。 在用于制造包括基台的牙科植入物的方法中,通过包括用于模制钛成型体组合物的钛成型体制造步骤以获得具有阳螺纹部分和阴螺纹部分之一的钛成型体的步骤制造基台, 用于模制陶瓷成型体组合物的模制体生产步骤,以获得具有与一个螺纹部分进行螺纹联接的另一螺纹部分的陶瓷模制体,将钛模制体和陶瓷模制体组装在一起的组装步骤, 一个螺纹部分与另一个螺纹部分进行螺纹联接,以获得组装体,用于使组装体脱脂的脱脂步骤,以及用于烧结组装体的烧结步骤,从而脱脂。

    SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER
    8.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER 审中-公开
    半导体器件,其中包括堆叠在一起的其他一些

    公开(公告)号:US20140177367A1

    公开(公告)日:2014-06-26

    申请号:US14189896

    申请日:2014-02-25

    申请人: Junichi HAYASHI

    发明人: Junichi HAYASHI

    IPC分类号: G11C11/403 H01L27/108

    摘要: A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips.

    摘要翻译: 一种设备包括通过硅通孔(TSV)连接的堆叠配置中的多个动态随机存取存储器(DRAM)芯片,并且所述多个DRAM芯片中的每一个被配置为提供本地存储体活动信号以指示何时 所述多个DRAM芯片中的相应一个DRAM芯片上的多个存储体是有效的,并且来自所述多个DRAM芯片的局部存储体活动信号通过所述多个DRAM芯片中的所述DRAM芯片的TSV被提供给所述多个DRAM芯片中的最下面的DRAM 筹码

    DELAY LOCK LOOP CIRCUIT AND SEMICONDUCTOR DEVICE
    9.
    发明申请
    DELAY LOCK LOOP CIRCUIT AND SEMICONDUCTOR DEVICE 审中-公开
    延迟锁定环路和半导体器件

    公开(公告)号:US20090251183A1

    公开(公告)日:2009-10-08

    申请号:US12416504

    申请日:2009-04-01

    申请人: Junichi HAYASHI

    发明人: Junichi HAYASHI

    IPC分类号: H03L7/06

    摘要: A simple circuit for preventing occurrence of a hazard and output delay for an asynchronous input signal in a clock signal. A flip-flop circuit (FF) outputs an output signal at a low level to a clocked inverter circuit (INVO) when a clock signal (PCLKB) transitions from a high level to a low level after an enabling signal (ENAT) goes to a high level. The clocked inverter circuit (INVO) is active when the clock signal (PCLKB) is at a low level, and inverts an output signal of the flip-flop circuit (FF) and outputs the output signal to a holding circuit (LATCH). The holding circuit (LATCH) holds the output signal of the clocked inverter circuit (INVO) and outputs the output signal as a signal (ENAOUT).

    摘要翻译: 用于防止在时钟信号中产生异步输入信号的危险和输出延迟的简单电路。 当使能信号(ENAT)变为“1”时,当时钟信号(PCLKB)从高电平转变为低电平时,触发器电路(FF)将低电平的输出信号输出到时钟反相器电路(INVO) 高水平。 时钟反相器电路(INVO)在时钟信号(PCLKB)处于低电平时有效,并且触发器电路(FF)的输出信号反相,并将输出信号输出到保持电路(LATCH)。 保持电路(LATCH)保持时钟反相器电路(INVO)的输出信号,并将输出信号作为信号(ENAOUT)输出。

    SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER
    10.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER 有权
    半导体器件,其中包括堆叠在一起的其他一些

    公开(公告)号:US20120195090A1

    公开(公告)日:2012-08-02

    申请号:US13358448

    申请日:2012-01-25

    IPC分类号: G11C5/06

    CPC分类号: G11C5/063 G11C5/02

    摘要: Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips.

    摘要翻译: 公开了这样的装置,其包括彼此堆叠的第一和第二芯片,以及控制堆叠在第一和第二芯片上的第一和第二芯片的第三芯片,并且包括第一,第二和第三输出电路。 第一输出电路向第一芯片提供第一命令信号。 第二输出电路将第一命令信号提供给第二芯片。 第三输出电路向第一和第二芯片提供第二命令信号。