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公开(公告)号：US10572378B2
公开(公告)日：2020-02-25
申请号：US15115307
申请日：2014-03-20
发明人： Sheng Li , Jichuan Chang , Jishen Zhao
IPC分类号： G06F12/02 , G06F12/08 , G06F3/06 , G06F12/0875 , G06F12/0893
摘要： Dynamic memory expansion based on data compression is described. Data represented in at least one page to be written to a main memory of a computing device is received. The data is compressed in the at least one page to generate at least one compressed physical page and a metadata entry corresponding to each page of the at least one compressed physical page. The metadata entry is cached in a metadata cache including metadata entries and pointers to the uncompressed region of the at least one compressed physical page.
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公开(公告)号：US20170004069A1
公开(公告)日：2017-01-05
申请号：US15115307
申请日：2014-03-20
发明人： Sheng Li , Jichuan Chang , Jishen Zhao
IPC分类号： G06F12/02 , G06F12/0893
CPC分类号： G06F12/023 , G06F3/0638 , G06F12/08 , G06F12/0875 , G06F12/0893 , G06F2212/1044 , G06F2212/401 , G06F2212/466 , G06F2212/608
摘要： Dynamic memory expansion based on data compression is described. Data represented in at least one page to be written to a main memory of a computing device is received. The data is compressed in the at least one page to generate at least one compressed physical page and a metadata entry corresponding to each page of the at least one compressed physical page. The metadata entry is cached in a metadata cache deluding metadata entries and pointers to the uncompressed region of the at least one compressed physical page.
摘要翻译： 描述了基于数据压缩的动态内存扩展。 接收在要写入计算设备的主存储器的至少一个页面中表示的数据。 所述数据在所述至少一个页面中被压缩以生成与所述至少一个压缩物理页面的每个页面相对应的至少一个压缩物理页面和元数据条目。 元数据条目被缓存在元数据高速缓存中，将元数据条目和指针指向至少一个压缩物理页面的未压缩区域。
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公开(公告)号：US20160342516A1
公开(公告)日：2016-11-24
申请号：US15113960
申请日：2014-01-31
发明人： Jichuan Chang , Sheng Li
IPC分类号： G06F12/0815 , G06F12/084
CPC分类号： G06F12/0815 , G06F12/0817 , G06F12/084 , G06F12/1027 , G06F2212/1032 , G06F2212/1041 , G06F2212/281
摘要： Methods and systems for providing cache coherence in multi-compute-engine systems are described herein. In on example, concise cache coherency directory (CDir) for providing cache coherence in the multi-compute-engine systems is described. The CDir comprises a common pattern aggregated entry for one or more cache lines from amongst a plurality of cache lines of a shared memory. The one or more cache lines that correspond to the common pattern aggregated entry are associated with a common sharing pattern from amongst a predetermined number of sharing patterns that repeat most frequently in the region.
摘要翻译： 这里描述了用于在多计算引擎系统中提供高速缓存一致性的方法和系统。 在例子中，描述了用于在多计算引擎系统中提供高速缓存一致性的简洁高速缓存一致性目录（CDir）。 CDir包括来自共享存储器的多个高速缓存行之中的一个或多个高速缓存行的公共模式聚合条目。 对应于公共模式聚合条目的一个或多个高速缓存行与在该区域中最常重复的预定数量的共享模式中的公共共享模式相关联。
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公开(公告)号：US10152247B2
公开(公告)日：2018-12-11
申请号：US15113824
申请日：2014-01-23
发明人： Sheng Li , Jishen Zhao , Jichuan Chang , Parthasarathy Ranganathan , Alistair Veitch , Kevin T. Lim , Mark Lillibridge
摘要： A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.
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公开(公告)号：US10127282B2
公开(公告)日：2018-11-13
申请号：US15305960
申请日：2014-04-30
发明人： Sheng Li , Kevin T. Lim , Dejan S. Milojicic , Paolo Faraboschi
摘要： A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.
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公开(公告)号：US20180074959A1
公开(公告)日：2018-03-15
申请号：US15320685
申请日：2014-07-22
发明人： Sheng Li , Jishen Zhao , Kevin T. Lim , Paolo Faraboschi
IPC分类号： G06F12/0815 , G06F1/32 , G06F13/40
CPC分类号： G06F12/0815 , G06F1/3287 , G06F1/3296 , G06F12/0806 , G06F13/14 , G06F13/4022 , G06F2212/1008 , G06F2212/62
摘要： According to an example, a node-based computing device includes memory nodes communicatively coupled to a processor node. The memory nodes may form a main memory address space for the processor node. The processor node may establish a virtual circuit through memory nodes. The virtual circuit may dedicate a path within the memory nodes. The processor node may then communicate a message through the virtual circuit. The memory nodes may forward the message according to the path dedicated by the virtual circuit.
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公开(公告)号：US20160253105A1
公开(公告)日：2016-09-01
申请号：US15032327
申请日：2013-10-31
IPC分类号： G06F3/06
摘要： A method for compressing and compacting memory on a memory device is described. The method includes organizing a number of compressed memory pages referenced in a number of compaction table entries based on a size of the number of compressed memory pages and compressing the number of compaction table entries, in which a compaction table entry comprise a number of fields.
摘要翻译： 描述了一种用于在存储器件上压缩和压缩存储器的方法。 该方法包括：基于压缩存储器页面的数量的大小来压缩多个压缩表条目中引用的多个压缩存储器页面，并且压缩压缩表条目的数量，其中压缩表条目包括多个字段。
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公开(公告)号：US10402324B2
公开(公告)日：2019-09-03
申请号：US15032329
申请日：2013-10-31
IPC分类号： G06F12/0802 , G06F13/38
摘要： According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
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公开(公告)号：US10241711B2
公开(公告)日：2019-03-26
申请号：US14774521
申请日：2013-03-14
发明人： Doe Hyun Yoon , Sheng Li , Jishen Zhao , Norman P. Jouppi
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0868 , G06F12/0897 , G06F9/46 , G06F12/0804 , G06F12/0815
摘要： Example methods and systems to provide persistent memory are disclosed herein. An example system includes a nonvolatile cache to store data received from a volatile cache. The data is associated with a transaction and the data is to be identified as durable when the transaction is committed. The example system includes a nonvolatile memory to store the data received from the nonvolatile cache when the data is identified as durable.
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公开(公告)号：US10127154B2
公开(公告)日：2018-11-13
申请号：US14764651
申请日：2013-03-20
发明人： Norman Paul Jouppi , Sheng Li , Ke Chen
IPC分类号： G06F13/00 , G06F12/0844 , G06F12/08 , G06F12/0811
摘要： A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.
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