公开(公告)号：US10127154B2

公开(公告)日：2018-11-13

申请号：US14764651

申请日：2013-03-20

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Norman Paul Jouppi ,  Sheng Li ,  Ke Chen

IPC分类号： G06F13/00 ,  G06F12/0844 ,  G06F12/08 ,  G06F12/0811

摘要： A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.

公开(公告)号：US10691344B2

公开(公告)日：2020-06-23

申请号：US14785120

申请日：2013-05-30

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Doe Hyun Yoon ,  Sheng Li ,  Jichuan Chang ,  Ke Chen ,  Parthasarathy Ranganathan ,  Norman Paul Jouppi

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

摘要： A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.