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公开(公告)号：US10241711B2
公开(公告)日：2019-03-26
申请号：US14774521
申请日：2013-03-14
发明人： Doe Hyun Yoon , Sheng Li , Jishen Zhao , Norman P. Jouppi
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0868 , G06F12/0897 , G06F9/46 , G06F12/0804 , G06F12/0815
摘要： Example methods and systems to provide persistent memory are disclosed herein. An example system includes a nonvolatile cache to store data received from a volatile cache. The data is associated with a transaction and the data is to be identified as durable when the transaction is committed. The example system includes a nonvolatile memory to store the data received from the nonvolatile cache when the data is identified as durable.
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公开(公告)号：US09846653B2
公开(公告)日：2017-12-19
申请号：US15120357
申请日：2014-02-21
发明人： Jichuan Chang , Doe Hyun Yoon , Robert Schreiber
IPC分类号： G06F12/08 , G06F12/0891 , G06F12/0862
CPC分类号： G06F12/0891 , G06F12/0862 , G06F2212/2024 , G06F2212/60 , G06F2212/6026
摘要： Write operations on main memory comprise predicting a last write in a dirty cache line. The predicted last write indicates a predicted pattern of the dirty cache line before the dirty cache line is evicted from a cache memory. Further, the predicted pattern is compared with a pattern of original data bits stored in the main memory for identifying changes to be made in the original data bits. Based on the comparison, an optimization operation to be performed on the original data bits is determined. The optimization operation modifies the original data bits based on the predicted pattern of a last write cache line before the last write cache line is evicted from the cache memory.
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公开(公告)号：US10585602B2
公开(公告)日：2020-03-10
申请号：US16011187
申请日：2018-06-18
摘要： An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.
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公开(公告)号：US09710335B2
公开(公告)日：2017-07-18
申请号：US14785421
申请日：2013-07-31
发明人： Doe Hyun Yoon , Terence P. Kelly , Jichuan Chang , Naveen Muralimanohar , Robert Schreiber , Parthasarathy Ranganathan
CPC分类号： G06F11/1451 , G06F3/0614 , G06F3/0628 , G06F11/1072 , G06F11/1435 , G06F11/1471 , G06F2201/84 , G11C29/52
摘要： According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
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公开(公告)号：US10691344B2
公开(公告)日：2020-06-23
申请号：US14785120
申请日：2013-05-30
发明人： Doe Hyun Yoon , Sheng Li , Jichuan Chang , Ke Chen , Parthasarathy Ranganathan , Norman Paul Jouppi
摘要： A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
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公开(公告)号：US10318365B2
公开(公告)日：2019-06-11
申请号：US14437684
申请日：2012-11-02
发明人： Sheng Li , Norman P. Jouppi , Doe Hyun Yoon
IPC分类号： G06F11/00 , G06F11/07 , G11C29/42 , G11C29/02 , G11C29/52 , G06F11/10 , G06F12/0875 , G11C7/20 , G11C29/04
摘要： Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.
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公开(公告)号：US20180307420A1
公开(公告)日：2018-10-25
申请号：US16011187
申请日：2018-06-18
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0655 , G06F3/0656 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F11/108 , G06F2211/1054 , G06F2211/1066
摘要： An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.
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公开(公告)号：US10019176B2
公开(公告)日：2018-07-10
申请号：US14417220
申请日：2012-10-30
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/0655 , G06F3/0656 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F11/108 , G06F2211/1054 , G06F2211/1066
摘要： An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.
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公开(公告)号：US09575542B2
公开(公告)日：2017-02-21
申请号：US13755527
申请日：2013-01-31
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.
摘要翻译： 功率管理模块可以基于针对每个操作模式确定的应用性能和总计算机系统功耗，来选择计算机系统中的硬件组件的多种不同操作模式之一。
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