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公开(公告)号：US12093730B2
公开(公告)日：2024-09-17
申请号：US18476690
申请日：2023-09-28
CPC分类号： G06F9/4881 , G06F9/5005 , G06F9/5044 , G06F9/505 , G06F9/5055
摘要： Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.
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公开(公告)号：US11853846B2
公开(公告)日：2023-12-26
申请号：US17044633
申请日：2018-04-30
发明人： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , John Paul Strachan , Sergey Serebryakov
CPC分类号： G06N3/08 , G11C13/0069 , G11C2213/77
摘要： A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
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公开(公告)号：US11809218B2
公开(公告)日：2023-11-07
申请号：US17198871
申请日：2021-03-11
CPC分类号： G06F9/4881 , G06F9/505 , G06F9/5005 , G06F9/5044 , G06F9/5055
摘要： Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.
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公开(公告)号：US11385863B2
公开(公告)日：2022-07-12
申请号：US16052218
申请日：2018-08-01
发明人： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , Sergey Serebryakov , John Paul Strachan
摘要： Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.
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公开(公告)号：US10649829B2
公开(公告)日：2020-05-12
申请号：US15645105
申请日：2017-07-10
摘要： In some examples, a controller includes a counter to track errors associated with a group of memory access operations, and processing logic to detect an error associated with the group of memory access operations, determine whether the detected error causes an error state change of the group of memory access operations, and cause advancing of the counter responsive to determining that the detected error causes the error state change of the group of memory access operations.
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公开(公告)号：US10572150B2
公开(公告)日：2020-02-25
申请号：US14784245
申请日：2013-04-30
摘要： According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
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公开(公告)号：US10324722B2
公开(公告)日：2019-06-18
申请号：US15192742
申请日：2016-06-24
摘要： Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
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公开(公告)号：US20180349051A1
公开(公告)日：2018-12-06
申请号：US15776473
申请日：2016-02-05
IPC分类号： G06F3/06 , G06F12/0815
CPC分类号： G06F13/1663 , Y02D10/14
摘要： A computing device includes a coherence controller and memory comprising a coherent memory region and a non-coherent memory region. The coherence controller may: determine a coherent region of the memory, determine a non-coherent region of the memory, and responsive to receiving a memory allocation request for a block of memory in the memory: allocate, based on a received memory allocation request for a memory block, the requested block of memory in the non-coherent memory region or the coherent memory region based on whether the memory allocation request indicates the requested block is to be coherent or non-coherent.
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公开(公告)号：US20180217929A1
公开(公告)日：2018-08-02
申请号：US15746618
申请日：2015-07-30
CPC分类号： G06F12/0607 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0673 , G06F2212/1016 , G06F2212/1024
摘要： In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
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公开(公告)号：US20170371663A1
公开(公告)日：2017-12-28
申请号：US15192742
申请日：2016-06-24
CPC分类号： G06F9/30145 , G06F12/0223 , G06F13/1668 , G06F2212/254
摘要： Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
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