公开(公告)号：US07668031B2

公开(公告)日：2010-02-23

申请号：US11967531

申请日：2007-12-31

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C7/02

CPC分类号： G11C7/14 ,  G11C11/22

摘要： A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 半导体存储器件包括连接在一对位线之间并由字线控制的单晶体管（1-T）场效应晶体管（FET）型存储单元，其中不同的沟道电阻被引导到通道区域依赖 在铁电层的极性状态。 该装置包括排列成行方向的多个字线，沿列方向配置的多个位线，沿列方向排列的一对钳位虚拟线，沿列方向排列的一对基准虚拟线， 包括存储单元并形成在字线和位线交叉的区域中的单元阵列，包括存储单元的虚拟单元阵列，并形成在字线，一对声线虚拟线和一对参考虚线之间 以及连接到位线并被配置为接收钳位电压和参考电压的读出放大器和写入驱动单元。

公开(公告)号：US07663910B2

公开(公告)日：2010-02-16

申请号：US12135241

申请日：2008-06-09

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.

摘要翻译： 相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。 多个基准位线和多个钳位位线在列方向上排列。 布置包括相变电阻单元的单元阵列块，其中字线和位线相交。 形成参考单元阵列块，其中字线和参考位线相交。 参考单元阵列块被配置为输出参考电流。 形成钳位单元阵列块，其中字线和钳位位线相交。 钳位单元阵列块被配置为输出钳位电流。 感测放大器连接到每个位线，并且被配置为接收钳位电压和参考电压。

公开(公告)号：US20100020622A1

公开(公告)日：2010-01-28

申请号：US12575343

申请日：2009-10-07

申请人： Hee Bok KANG ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok KANG ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C5/14 ,  G11C7/02

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10844 ,  H01L29/7841

摘要： A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 包括连接在位线和源极线之间并由字线控制的浮体存储元件的单晶体管型DRAM包括排列成行方向的多条源极线和字线， 列方向，沿列方向布置的多个钳位位线和参考位线，包括浮体存储元件并形成在源极线，字线和位线交叉的区域中的单元阵列，钳位 包括浮体存储元件并形成在源极线，字线和位线交叉的区域的单元阵列，包括浮体存储元件的参考单元阵列，并形成在源极线，字线 线和位线交叉，读出放大器和写入驱动单元连接到位线并被配置为接收钳位电压和参考电压。

公开(公告)号：US08319642B2

公开(公告)日：2012-11-27

申请号：US12135262

申请日：2008-06-09

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G08B13/14

CPC分类号： G06K19/07749

摘要： A RFID device having an analog block, a digital block, and a memory block having a nonvolatile ferroelectric memory is presented. The analog block is configured to receive a radio frequency signal so as to output an operating command signal. The digital block is configured to generate and output an address and an operation adjusting signal in response to the operating command signal. The digital block is also configured to output a response signal to the analog block and to generate a flag data corresponding to a data processing state and value. The memory block is configured to read and write a data in a nonvolatile ferroelectric capacitor in response to the operation adjusting signal. The memory block includes a memory unit configured to store the flag data so as to output the flag data to the digital block.

摘要翻译： 本发明提供一种具有模拟块，数字块和具有非易失性铁电存储器的存储块的RFID装置。 模拟块被配置为接收射频信号以输出操作命令信号。 数字块被配置为响应于操作命令信号产生并输出地址和操作调整信号。 数字模块还被配置为向模拟块输出响应信号，并产生对应于数据处理状态和值的标志数据。 存储器块被配置为响应于操作调整信号而在非易失性铁电电容器中读取和写入数据。 存储块包括被配置为存储标志数据以便将标志数据输出到数字块的存储器单元。

公开(公告)号：US08274369B2

公开(公告)日：2012-09-25

申请号：US12147675

申请日：2008-06-27

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： H04Q5/22

CPC分类号： H04Q9/00 ,  H04Q2209/47 ,  H04Q2209/84

摘要： A RFID device having a nonvolatile ferroelectric memory includes an analog block. A power-on reset unit configured to sense a power voltage and output a power sensing signal is included in the analog block. A radio frequency signal sensing unit is configured to sense the level of a detecting signal corresponding to a radio frequency signal received by the antenna of the RFID device and outputs a radio frequency sensing signal. A power-on reset mixer is configured to synthesize the power sensing signal and the radio frequency sensing signal and outputs a power-on reset signal according to the voltage levels of the power sensing signal and the radio frequency sensing signal.

摘要翻译： 具有非易失性铁电存储器的RFID装置包括模拟块。 配置为感测电源电压并输出功率感测信号的上电复位单元包括在模拟块中。 射频信号感测单元被配置为感测与由RFID设备的天线接收的射频信号相对应的检测信号的电平，并输出射频感测信号。 上电复位混频器被配置为合成功率感测信号和射频感测信号，并根据功率检测信号和射频感测信号的电压电平输出上电复位信号。

公开(公告)号：US07969794B2

公开(公告)日：2011-06-28

申请号：US12575343

申请日：2009-10-07

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C7/10

CPC分类号： H01L27/10802 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10844 ,  H01L29/7841

摘要： A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

摘要翻译： 包括连接在位线和源极线之间并由字线控制的浮体存储元件的单晶体管型DRAM包括排列成行方向的多条源极线和字线， 列方向，沿列方向布置的多个钳位位线和参考位线，包括浮体存储元件并形成在源极线，字线和位线交叉的区域中的单元阵列，钳位 包括浮体存储元件并形成在源极线，字线和位线交叉的区域的单元阵列，包括浮体存储元件的参考单元阵列，并形成在源极线，字线 线和位线交叉，读出放大器和写入驱动单元连接到位线并被配置为接收钳位电压和参考电压。

公开(公告)号：US07929339B2

公开(公告)日：2011-04-19

申请号：US12645704

申请日：2009-12-23

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： C11C11/00

CPC分类号： G11C13/0038 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

摘要： A phase change memory device includes a plurality of word lines arranged in a row direction and a plurality of bit lines arranged in a column direction. A plurality of reference bit line and a plurality of clamp bit lines are arranged in the column direction. A cell array block including a phase change resistance cell is arranged where a word line and a bit line intersect. A reference cell array block is formed where a word line and the reference bit line intersect. The reference cell array block is configured to output a reference current. A clamp cell array block is formed where a word line and a clamp bit line intersect. The clamp cell array block is configured to output a clamp current. A sense amplifier is connected to each of the bit lines and is configured to receive a clamp voltage and a reference voltage.

摘要翻译： 相变存储器件包括沿行方向布置的多个字线和沿列方向布置的多个位线。 多个基准位线和多个钳位位线在列方向上排列。 布置包括相变电阻单元的单元阵列块，其中字线和位线相交。 形成参考单元阵列块，其中字线和参考位线相交。 参考单元阵列块被配置为输出参考电流。 形成钳位单元阵列块，其中字线和钳位位线相交。 钳位单元阵列块被配置为输出钳位电流。 感测放大器连接到每个位线，并且被配置为接收钳位电压和参考电压。

公开(公告)号：US07864611B2

公开(公告)日：2011-01-04

申请号：US12609649

申请日：2009-10-30

申请人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2211/4016

摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

摘要翻译： 单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和 形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列 输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和 写入驱动单元连接到位线并被配置为接收多个参考电压。

公开(公告)号：US07643336B2

公开(公告)日：2010-01-05

申请号：US11987758

申请日：2007-12-04

申请人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Suk Kyoung Hong

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/72

摘要： A phase change memory device comprises a cell array unit including a phase change resistance cell disposed in a region where a word line and a bit line are crossed, a sense amplifier configured to sense and amplify data of the phase change resistance cell, a write driving unit configured to supply a write voltage corresponding to data to be written in the cell array unit in response to an enabling signal, and a write verifying control unit controlled by an activation control signal and configured to compare data read through the sense amplifier with the data to be written so as to output the enabling signal.

摘要翻译： 相变存储器件包括：单元阵列单元，包括设置在字线和位线交叉的区域中的相变电阻单元，被配置为感测和放大相变电阻单元的数据的读出放大器，写入驱动 单元，被配置为响应于使能信号提供与要写入单元阵列单元的数据相对应的写入电压;以及写入验证控制单元，其由激活控制信号控制，并且被配置为将通过读出放大器读取的数据与数据进行比较 被写入以输出使能信号。

公开(公告)号：US07630262B2

公开(公告)日：2009-12-08

申请号：US12003923

申请日：2008-01-03

申请人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

发明人： Hee Bok Kang ,  Jin Hong An ,  Sung Joo Hong ,  Suk Kyoung Hong

IPC分类号： G11C7/02

CPC分类号： G11C11/404 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2211/4016

摘要： A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages.

摘要翻译： 单晶体管型DRAM包括连接在位线和源极线之间并由字线控制的浮体存储元件。 DRAM包括沿行方向布置的多个源极线和字线，沿列方向布置的多个位线，沿列方向布置的多个参考位线，包括浮体存储元件的单元阵列和 形成在源极线，字线和位线交叉的区域中，形成在源极线，字线和位线交叉配置的区域中的包括浮体存储元件的基准单元阵列 输出具有多个电平的参考电流;多个参考电压产生单元，连接到参考位线并被配置为产生与具有多个电平的参考电流相对应的多个参考电压;以及读出放大器和 写入驱动单元连接到位线并被配置为接收多个参考电压。