METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME
    4.
    发明申请
    METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
    形成门结构的方法和使用其制造半导体器件的方法

    公开(公告)号:US20120034752A1

    公开(公告)日:2012-02-09

    申请号:US13195521

    申请日:2011-08-01

    Abstract: In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics.

    Abstract translation: 在形成栅极结构的方法中,形成包括依次层叠在基板上的栅极绝缘层图案和栅电极的栅极图案。 栅电极包括金属。 使用反应气体对栅极图案进行第一等离子体处理,以减少栅电极的氧化边缘部分。 反应气体包括氮气。 在栅极图案的侧壁上形成间隔物。 通过减小栅电极的氧化边缘部分来调节阈值电压。 因此,包括栅极图案的半导体器件具有优异的电气特性。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS
    5.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS 审中-公开
    用不同绝缘栅绝缘体制作半导体器件的方法

    公开(公告)号:US20110306171A1

    公开(公告)日:2011-12-15

    申请号:US13105652

    申请日:2011-05-11

    CPC classification number: H01L21/823857 H01L21/28202 H01L29/518

    Abstract: An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.

    Abstract translation: 在其上限定有NMOS区和PMOS区的基板上形成绝缘层。 在PMOS区域中的绝缘层上形成第一导电层,使NMOS区域中的绝缘层的一部分露出。 进行氮化,以在NMOS区域中的绝缘层中产生第一氮浓度,并且在PMOS区域中的绝缘层中小于第一氮浓度的第二氮浓度。 第二导电层形成在绝缘层上,并且第一导电层以及第一和第二导电层和绝缘层被图案化以分别在NMOS区域和PMOS区域中形成第一栅极结构和第二栅极结构。

    Formation of a high-K crystalline dielectric composition
    10.
    发明授权
    Formation of a high-K crystalline dielectric composition 有权
    形成高K结晶介电组合物

    公开(公告)号:US08476155B1

    公开(公告)日:2013-07-02

    申请号:US12835790

    申请日:2010-07-14

    Abstract: Provided are a method of forming a dielectric and a method of fabricating a semiconductor device. The method includes forming a preliminary dielectric including Hf, O and an “A” element on an underlying layer. The preliminary dielectric is formed in an amorphous structure or a mixed structure of an amorphous structure and an “M” crystalline structure. The “A” element about 1 at % to about 5 at % of the total content of the “A” element and Hf in the preliminary dielectric. Through a nitridation process, nitrogen is added to the preliminary dielectric. The nitrogen-containing dielectric is changed into a dielectric having a “T” crystalline structure through a phase transition process, wherein the “T” crystalline structure is different from the “M” crystalline structure. An upper layer is formed on the “T” crystalline dielectric.

    Abstract translation: 提供形成电介质的方法和制造半导体器件的方法。 该方法包括在下层上形成包含Hf,O和“A”元素的预备电介质。 预置电介质形成为非晶结构或非晶结构和“M”晶体结构的混合结构。 “A”元素在“A”元素的总含量和预置电介质中的Hf的约1at%至约5at%的“A”元素。 通过氮化处理,将氮气加入到初步电介质中。 通过相变过程将含氮电介质变成具有“T”晶体结构的电介质,其中“T”晶体结构不同于“M”晶体结构。 在“T”晶体电介质上形成上层。

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