知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.015 seconds)

    SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICES EMPLOYING HIGH-K DIELECTRIC LAYERS AS A GATE INSULATING LAYER AND METHODS OF FABRICATING THE SAME 有权
    使用高K介电层作为绝缘层的半导体器件及其制造方法

    公开(公告)号：US20120129330A1

    公开(公告)日：2012-05-24

    申请号：US13240327

    申请日：2011-09-22

    Applicant: WeonHong KIM ,  Dae-Kwon Joo

    Inventor： WeonHong KIM ,  Dae-Kwon Joo

    IPC: H01L21/28

    CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

    Abstract translation: 一种制造半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成含氮下部栅极绝缘层，在含氮的下部栅极绝缘层上形成上部栅极绝缘层， 在上栅极绝缘层上形成下金属层; 并且选择性地去除第一区域中的下金属层，使得下部金属层图案保留在第二区域中，其中第一区域中的上栅极绝缘层防止在去除第一区域期间第一区域中的下栅极绝缘层被蚀刻 第一区域中的下金属层。 还提供了通过该方法制造的半导体器件。

    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS
    6.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH DIFFERENTIALLY NITRIDED GATE INSULATORS 审中-公开
    用不同绝缘栅绝缘体制作半导体器件的方法

    公开(公告)号：US20110306171A1

    公开(公告)日：2011-12-15

    申请号：US13105652

    申请日：2011-05-11

    Applicant: Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

    Inventor： Ha-Jin Lim ,  Jin-Ho Do ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Dae-Kwon Joo

    IPC: H01L21/8238 ,  H01L21/28

    CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L29/518

    Abstract: An insulation layer is formed on a substrate having an NMOS region and a PMOS region defined therein. A first conductive layer is formed on the insulation layer in the PMOS region, leaving a portion of the insulation layer in the NMOS region exposed. Nitriding is performed to produce a first nitrogen concentration in the insulation layer in the NMOS region and a second nitrogen concentration less than the first nitrogen concentration in the insulation layer in the PMOS region. A second conductive layer is formed on the insulation layer and the first conductive layer and the first and second conductive layers and the insulation layer are patterned to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively.

    Abstract translation: 在其上限定有NMOS区和PMOS区的基板上形成绝缘层。 在PMOS区域中的绝缘层上形成第一导电层，使NMOS区域中的绝缘层的一部分露出。 进行氮化，以在NMOS区域中的绝缘层中产生第一氮浓度，并且在PMOS区域中的绝缘层中小于第一氮浓度的第二氮浓度。 第二导电层形成在绝缘层上，并且第一导电层以及第一和第二导电层和绝缘层被图案化以分别在NMOS区域和PMOS区域中形成第一栅极结构和第二栅极结构。

    Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same
    8.
    发明授权
    Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same 有权
    采用高K电介质层作为栅极绝缘层的半导体器件及其制造方法

    公开(公告)号：US08652908B2

    公开(公告)日：2014-02-18

    申请号：US13240327

    申请日：2011-09-22

    Applicant: WeonHong Kim ,  Dae-Kwon Joo

    Inventor： WeonHong Kim ,  Dae-Kwon Joo

    IPC: H01L21/8238 ,  H01L21/4763

    CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a nitrogen-containing lower gate insulating layer on the semiconductor substrate, forming an upper gate insulating layer on the nitrogen containing lower gate insulating layer, forming a lower metal layer on the upper gate insulating layer; and selectively removing the lower metal layer in the first region such that a lower metal layer pattern remains in the second region, wherein the upper gate insulating layer in the first region prevents the lower gate insulating layer in the first region from being etched during removing of the lower metal layer in the first region. A semiconductor device fabricated by the method is also provided.

    Abstract translation: 一种制造半导体器件的方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成含氮下部栅极绝缘层，在含氮的下部栅极绝缘层上形成上部栅极绝缘层， 在上栅极绝缘层上形成下金属层; 并且选择性地去除第一区域中的下金属层，使得下部金属层图案保留在第二区域中，其中第一区域中的上栅极绝缘层防止在去除第一区域期间第一区域中的下栅极绝缘层被蚀刻 第一区域中的下金属层。 还提供了通过该方法制造的半导体器件。

    Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same 有权
    包括具有优化沟道区的MOS晶体管的半导体器件及其制造方法

    公开(公告)号：US08575705B2

    公开(公告)日：2013-11-05

    申请号：US12964173

    申请日：2010-12-09

    Applicant: Hajin Lim ,  Myungsun Kim ,  Hoi Sung Chung ,  Jinho Do ,  Weonhong Kim ,  Moonkyun Song ,  Dae-Kwon Joo

    Inventor： Hajin Lim ,  Myungsun Kim ,  Hoi Sung Chung ,  Jinho Do ,  Weonhong Kim ,  Moonkyun Song ,  Dae-Kwon Joo

    IPC: H01L21/70

    CPC classification number: H01L21/823807 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

    Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.

    Abstract translation: 一种半导体器件，包括布置在半导体衬底的预定区域上以限定有源区的器件隔离层，所述有源区包括（100）晶面的中心顶表面和从中心顶表面延伸的倾斜边缘表面 到所述器件隔离层，覆盖所述有源区的中心顶表面和倾斜边缘表面的半导体图案，所述半导体图案包括与所述有源区的中心顶表面平行的（100）晶面的平坦顶表面 区域和基本上垂直于平坦顶表面的侧壁以及与半导体图案重叠的栅极图案。

Patent Agency Ranking