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    Dimension-controlled via formation processing
    1.
    发明授权
    Dimension-controlled via formation processing 有权
    尺寸控制通过形成处理

    公开(公告)号：US09305832B2

    公开(公告)日：2016-04-05

    申请号：US14315659

    申请日：2014-06-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiang Hu ,  Yuping Ren ,  Duohui Bei ,  Sipeng Gu ,  Huang Liu

    IPC: H01L21/308 ,  H01L21/768 ,  H01L21/033 ,  H01L23/538 ,  H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

    Abstract translation: 提供了用于在电路结构上的尺寸控制的通孔形成的方法，包括在多个相邻的导电结构上。 所述方法包括例如在电路结构之上提供图案化的多层堆叠结构，所述堆叠结构包括至少一层，以及在所述至少一层上方的图案转移层，所述图案转移层被图案化 至少有一个通孔; 在所述至少一个通孔开口内提供侧壁间隔层，以形成至少一个尺寸控制的通孔开口; 以及使用所述至少一个尺寸控制的通孔开口蚀刻穿过所述堆叠结构的所述至少一个层，以便于在所述电路结构上提供通孔。 在一个实施方案中，堆叠结构包括设置在电介质层和平坦化层之间的图案化硬掩模层内的沟槽开口，并且通孔部分地自对准沟槽。

    Methods of facilitating fabricating transistors
    3.
    发明授权
    Methods of facilitating fabricating transistors 有权
    促进制造晶体管的方法

    公开(公告)号：US09425100B1

    公开(公告)日：2016-08-23

    申请号：US14694276

    申请日：2015-04-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Zhaoxu Shen ,  Min-hwa Chi ,  Haiting Wang ,  Qin Wang ,  Meixiong Zhao ,  Duohui Bei

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/306 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

    CPC classification number: H01L21/823412 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

    Abstract: Methods and transistors for circuit structures are provided. The methods include, for instance: defining a channel region in a substrate, the channel region having at least one channel region sidewall adjoining an isolation material; recessing the isolation material to expose an upper portion of the at least one channel region sidewall; and providing a gate structure over a gate interface area with the channel region. The gate interface area includes at least the upper portion of the at least one channel region sidewall and an upper surface of the channel region so that a threshold voltage of the gate structure may be reduced. The methods may also include etching an elongate notch in the upper portion of the at least one channel region sidewall to increase a size of the gate interface area and further reduce the threshold voltage of the gate structure.

    Abstract translation: 提供了用于电路结构的方法和晶体管。 所述方法包括例如：在衬底中限定沟道区，所述沟道区具有邻近隔离材料的至少一个沟道区侧壁; 使隔离材料凹陷以暴露至少一个通道区域侧壁的上部; 以及在与沟道区域的栅极接口区域上提供栅极结构。 栅极界面区域至少包括至少一个沟道区域侧壁的上部和沟道区域的上表面，使得可以减小栅极结构的阈值电压。 所述方法还可以包括蚀刻在所述至少一个沟道区域侧壁的上部中的细长凹口以增加栅极界面面积的尺寸并进一步降低栅极结构的阈值电压。

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