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    Selective spacer formation on transistors of different classes on the same device
    1.
    发明授权
    Selective spacer formation on transistors of different classes on the same device 有权
    在同一器件上的不同类晶体管上的选择性间隔物形成

    公开(公告)号：US07541239B2

    公开(公告)日：2009-06-02

    申请号：US11479762

    申请日：2006-06-30

    申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    IPC分类号： H01L21/8238 ,  H01L31/119

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

    摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

    Selective spacer formation on transistors of different classes on the same device
    3.
    发明授权
    Selective spacer formation on transistors of different classes on the same device 有权
    在同一器件上的不同类晶体管上的选择性间隔物形成

    公开(公告)号：US08154067B2

    公开(公告)日：2012-04-10

    申请号：US12419242

    申请日：2009-04-06

    申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    IPC分类号： H01L31/119 ,  H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

    摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

    SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE
    4.
    发明申请
    SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE 有权
    在相同设备上的不同类别的晶体管上形成选择间隔

    公开(公告)号：US20110157854A1

    公开(公告)日：2011-06-30

    申请号：US13040951

    申请日：2011-03-04

    申请人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    IPC分类号： H05K7/00

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

    摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

    SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE
    5.
    发明申请
    SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE 有权
    在相同设备上的不同类别的晶体管上形成选择间隔

    公开(公告)号：US20090189193A1

    公开(公告)日：2009-07-30

    申请号：US12419242

    申请日：2009-04-06

    申请人： GIUSEPPE CURELLO ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    发明人： GIUSEPPE CURELLO ,  Ian R. Post ,  Chia-Hong Jan ,  Mark Bohr

    IPC分类号： H01L27/10

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

    摘要： A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.

    摘要翻译： 在通过这种方法形成的第一类晶体管和器件上选择性地形成间隔物的方法。 该方法可以包括在其上具有不同类别的晶体管的衬底上沉积共形第一沉积层，将沉积层分隔成至少一类晶体管，干蚀刻第一沉积层，去除阻挡层，沉积保形第二沉积 在所述衬底上干燥蚀刻所述第二沉积层并湿蚀刻剩余的第一沉积层。 与第二类晶体管的间隔物相比，器件可以包括具有较大间隔物的第一类晶体管。

    Penetrating implant for forming a semiconductor device
    8.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08426927B2

    公开(公告)日：2013-04-23

    申请号：US13107783

    申请日：2011-05-13

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Penetrating implant for forming a semiconductor device
    9.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US07943468B2

    公开(公告)日：2011-05-17

    申请号：US12059455

    申请日：2008-03-31

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。