发明申请
US20090189193A1 SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE
有权
在相同设备上的不同类别的晶体管上形成选择间隔
- 专利标题: SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE
- 专利标题(中): 在相同设备上的不同类别的晶体管上形成选择间隔
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申请号: US12419242申请日: 2009-04-06
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公开(公告)号: US20090189193A1公开(公告)日: 2009-07-30
- 发明人: GIUSEPPE CURELLO , Ian R. Post , Chia-Hong Jan , Mark Bohr
- 申请人: GIUSEPPE CURELLO , Ian R. Post , Chia-Hong Jan , Mark Bohr
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L27/10
- IPC分类号: H01L27/10
摘要:
A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
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