Invention Grant
- Patent Title: Selective spacer formation on transistors of different classes on the same device
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Application No.: US13040951Application Date: 2011-03-04
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Publication No.: US08174060B2Publication Date: 2012-05-08
- Inventor: Giuseppe Curello , Ian R. Post , Chia-Hong Jan , Mark Bohr
- Applicant: Giuseppe Curello , Ian R. Post , Chia-Hong Jan , Mark Bohr
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L31/119
- IPC: H01L31/119 ; H01L21/8238

Abstract:
A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.
Public/Granted literature
- US20110157854A1 SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE Public/Granted day:2011-06-30
Information query
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