公开(公告)号：US20150149746A1

公开(公告)日：2015-05-28

申请号：US14536763

申请日：2014-11-10

Applicant: FUJITSU LIMITED

Inventor： Makoto SUGA ,  AKIO TOKOYODA ,  Koji HOSOE ,  Masatoshi Aihara ,  Yuta Toyoda

IPC: G06F9/30

CPC classification number: G06F12/00 ,  G06F9/30043 ,  G06F9/3824 ,  G06F12/023 ,  G06F13/00 ,  G06F2212/1024 ,  G06F2212/401 ,  G06F2212/502

Abstract: An arithmetic processing device promotes transmission efficiency between a processor and a memory. The arithmetic processing device has an arithmetic processing unit which issues an instruction accompanying with data which is sent to the memory, a judgment unit which judges whether or not a redundancy degree of the data which is accompanied with the instruction is more than a predetermined value, a compression unit which judges whether or not compress the data based on an waiting time and a compression time when the redundancy degree of the data is more than the predetermined value, and compress the data when judging that performs the compression, and an instruction arbitration unit which transfers the instruction accompanying with the compressed data to the memory when the compression unit performs the compression and transfers the instruction accompanying with the non-compressed data to the memory when the compression unit does not perform the compression.

Abstract translation: 算术处理装置提高处理器和存储器之间的传输效率。 算术处理装置具有运算处理单元，该运算处理单元发出伴随着发送给存储器的数据的指令，判断单元判断伴随该指令的数据的冗余度是否大于预定值， 压缩单元，其基于当数据的冗余度大于预定值时的等待时间和压缩时间来判断是否压缩数据，并且在执行压缩的判定时压缩数据;以及指令仲裁单元 当压缩单元执行压缩时，将压缩数据附带的指令传送到存储器，并且当压缩单元不执行压缩时，将伴随非压缩数据的指令传送到存储器。

公开(公告)号：US20160350196A1

公开(公告)日：2016-12-01

申请号：US15150474

申请日：2016-05-10

Applicant: FUJITSU LIMITED

Inventor： Makoto SUGA ,  AKIO TOKOYODA ,  Masatoshi Aihara ,  Koji HOSOE ,  KOICHIRO TAKAYAMA

IPC: G06F11/273

CPC classification number: G06F11/00 ,  G06F2201/805 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/36 ,  G11C29/44 ,  G11C29/46 ,  G11C2029/2602 ,  G11C2029/3602 ,  G11C2029/4402 ,  G11C2029/5604

Abstract: The arithmetic processing device includes a first memory control unit configured to control an access to a first memory, a second memory control unit configured to control an access to a second memory. The arithmetic processing device further includes a diagnostic control unit configured to sequentially diagnose parts within the first memory via the first memory control unit, and configured to sequentially store in the second memory via the second memory control unit, diagnostic results of sequentially diagnosing the parts in parallel with the diagnosing the parts via the first memory control unit.

Abstract translation: 算术处理装置包括被配置为控制对第一存储器的访问的第一存储器控制单元，被配置为控制对第二存储器的访问的第二存储器控制单元。 所述算术处理装置还包括：诊断控制部，被配置为经由所述第一存储器控制部对所述第一存储器内的各部分顺序进行诊断，并且经由所述第二存储器控制部顺序地存储在所述第二存储器中， 与通过第一存储器控制单元诊断部件并行。

公开(公告)号：US20160098212A1

公开(公告)日：2016-04-07

申请号：US14847360

申请日：2015-09-08

Applicant: FUJITSU LIMITED

Inventor： AKIO TOKOYODA ,  Koji HOSOE ,  Masatoshi Aihara ,  Yuta Toyoda ,  Makoto SUGA

IPC: G06F3/06

CPC classification number: G11C7/00 ,  G06F13/1642

Abstract: An information processor apparatus includes: a storage device to perform processing based on a read request or a write request and output a response after completing the processing; an arithmetic processor to output the read and write requests to the storage device; and a control device, including paths, to control the storage device; the control device: receives the read request or the write request from the arithmetic processor; acquires, for each of the paths, an overall time until the response to a transmitted read and write requests is received based on a first number of the transmitted read requests and a second number of the transmitted write requests, selects a used path based on the overall time; transmits the read request or the write request through the used path to the storage device; and receives the response to the read request or the write request through the used path.

Abstract translation: 信息处理装置包括：存储装置，用于根据读取请求或写入请求执行处理，并在完成处理之后输出响应; 算术处理器，用于将读取和写入请求输出到存储设备; 以及包括路径的控制装置，以控制存储装置; 控制装置：从算术处理器接收读取请求或写入请求; 基于所发送的读取请求的第一数量和所发送的写入请求的第二数量，为每个路径获取整个时间，直到接收到发送的读取和写入请求的响应，基于 整体时间 通过使用的路径将读取请求或写入请求发送到存储设备; 并通过所使用的路径接收对读请求或写请求的响应。

公开(公告)号：US20190004896A1

公开(公告)日：2019-01-03

申请号：US16011685

申请日：2018-06-19

Applicant: FUJITSU LIMITED

Inventor： AKIO TOKOYODA

IPC: G06F11/10 ,  G06F12/06 ,  G06F12/0877

Abstract: A processor includes a memory-controller that controls an access to a memory which includes through electrode groups and a memory chip including a storage areas connected to each of the through-electrode groups including through-electrodes, and that includes an address-filter circuit that outputs an access address included in a read access request of reading data from the memory, as an error address, a counter that includes counters corresponding to the through-electrode groups and updates a counter value of the counter corresponding to the through-electrode group connected to the storage area indicated by the received error address, a first circuit that outputs area information indicating the storage area connected to the through-electrode group corresponding to the counter having a counter value which is greater than a predetermined value, and a second circuit that outputs an access request to the storage area indicated by the area information output from the first circuit.

公开(公告)号：US20150339062A1

公开(公告)日：2015-11-26

申请号：US14708331

申请日：2015-05-11

Applicant: FUJITSU LIMITED

Inventor： Yuta Toyoda ,  Koji HOSOE ,  Masatoshi Aihara ,  AKIO TOKOYODA ,  Makoto SUGA

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0859 ,  G06F12/0879 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/301 ,  G06F2212/50

Abstract: An arithmetic processing device which connects to a main memory, the arithmetic processor includes a cache memory which stores data, an arithmetic unit which performs an arithmetic operation for data stored in the cache memory, a first control device which controls the cache memory and outputs a first request which reads the data stored in the main memory, and a second control device which is connected to the main memory and transmits a plurality of second requests which are divided the first request output from the first control device, receives data corresponding to the plurality of second requests which is transmitted from the main memory and sends each of the data to the first control device.

Abstract translation: 一种连接到主存储器的算术处理装置，所述算术处理器包括存储数据的高速缓存存储器，对存储在所述高速缓冲存储器中的数据执行算术运算的算术单元，控制所述高速缓冲存储器并输出 第一请求，其读取存储在主存储器中的数据;以及第二控制装置，其连接到主存储器，并且发送分配了从第一控制装置输出的第一请求的多个第二请求，接收与多个 从主存储器发送的第二请求，并将每个数据发送到第一控制装置。

公开(公告)号：US20150149675A1

公开(公告)日：2015-05-28

申请号：US14542730

申请日：2014-11-17

Applicant: FUJITSU LIMITED

Inventor： Yuta Toyoda ,  Koji HOSOE ,  AKIO TOKOYODA ,  Masatoshi Aihara ,  Makoto SUGA

IPC: G06F13/16 ,  G06F13/366

CPC classification number: G06F13/1605 ,  G06F13/161 ,  G06F13/366

Abstract: A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first.

Abstract translation: 存储器控制器具有保持写请求和读请求的请求保持单元; 发送单元，通过发送总线将写入请求和读取请求中的任一个发送到存储器; 接收单元，通过接收总线接收对应于读取请求的读取数据; 以及请求仲裁单元，执行：当第一接收时间不晚于第二接收时间时，在所述读取请求之前发送所述写入请求的第一处理，以及在所述写入请求之前发送所述读取请求的第二处理， 第一接收时间晚于第二接收时间。 第一接收时间是当首先发送写请求时开始读取数据的接收，并且第二接收时间是当首先发送读取请求时开始读取数据的接收。