公开(公告)号：US20250029916A1

公开(公告)日：2025-01-23

申请号：US18903703

申请日：2024-10-01

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryoichi KATO ,  Yoshinari IKEDA ,  Yuma MURATA

IPC: H01L23/522 ,  H01L23/49 ,  H01L23/498 ,  H01L25/16 ,  H01R4/02 ,  H01R43/02

Abstract: A semiconductor device includes a capacitor including a first connection terminal, a second connection terminal, and a second insulating member disposed between the first connection terminal and the second connection terminal, and a semiconductor module including a multi-layer terminal portion in which a first power terminal, a first insulating member, and a second power terminal are sequentially stacked. The first connection terminal and the second connection terminal extend to an outside, the first power terminal includes a first bonding area electrically connected to the first connection terminal, the second power terminal includes a second bonding area electrically connected to the second connection terminal, and the first insulating member includes a terrace portion extending from an end portion of the second power terminal toward the first connection terminal in a plan view of the semiconductor module.

公开(公告)号：US20230069967A1

公开(公告)日：2023-03-09

申请号：US17875851

申请日：2022-07-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Nobuhiro HIGASHI ,  Daiki YOSHIDA ,  Yuma MURATA ,  Naoyuki KANAI

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor apparatus includes a semiconductor element, a control terminal electrically connected to a top electrode of the semiconductor element through a wiring member, and a case member in which at least a portion of the control terminal is embedded and which defines a space for housing the semiconductor element. The control terminal includes a pad to which the wiring member is connected. The case member includes a wiring member positioning part raised on the case member as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad.

公开(公告)号：US20240222311A1

公开(公告)日：2024-07-04

申请号：US18605500

申请日：2024-03-14

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryoichi KATO ,  Yuichiro HINATA ,  Yuma MURATA

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L24/40 ,  H01L23/5386 ,  H01L24/37 ,  H01L24/73 ,  H01L25/072 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37655 ,  H01L2224/37663 ,  H01L2224/40091 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/0132 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor device including: first and second conductive portions having a gap therebetween; connection wiring including first and second bonding portions respectively bonded to front surfaces of the first and second conductive portions, and a wiring portion straddling the gap and connecting the first and second bonding portions; and a wire bonded to the wiring portion. The wiring portion includes: a vertical portion extending, from a lower end to an upper end thereof, perpendicularly to the first conductive portion, the lower end being connected to the first bonding portion; a parallel portion extending in parallel to the first and second conductive portions from the upper end of the vertical portion, the parallel portion having, on a front surface thereof, a wire bonding portion to which one end of the wire is bonded; and an inclined portion extending inclinedly from the parallel portion toward the second bonding portion.

公开(公告)号：US20220415729A1

公开(公告)日：2022-12-29

申请号：US17825300

申请日：2022-05-26

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryoichi KATO ,  Yuma MURATA ,  Naoyuki KANAI

IPC: H01L23/049 ,  H01L25/07 ,  H01L23/31 ,  H01L23/49 ,  H01L23/00

Abstract: There is provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where connection sections used for the connection to semiconductor elements are arranged. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have first surface sections on the side where the connection sections are arranged and second surface sections formed, on the side where the connection sections are not arranged, such that the peeling strength to the sealing resins is lower than that of the first surface sections.

公开(公告)号：US20220208652A1

公开(公告)日：2022-06-30

申请号：US17542949

申请日：2021-12-06

Applicant: Fuji Electric Co., Ltd.

Inventor： Yuichiro HINATA ,  Yuma MURATA ,  Naoyuki KANAI ,  Ryoichi KATO

IPC: H01L23/495 ,  H01R43/02 ,  H01L23/58 ,  H01G2/00

Abstract: A semiconductor module includes a resin case housing a semiconductor element; an insulating layer extending outward from the resin case; and a first external connection terminal extending outward from the resin case, arranged above the insulating layer so as to face the insulting layer, the first external connection terminal having a non-contact portion that is not in contact with the insulating layer in a thickness direction of the insulating layer at a position overlapping the insulating layer in a plan view.

公开(公告)号：US20210280549A1

公开(公告)日：2021-09-09

申请号：US17185953

申请日：2021-02-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryoichi KATO ,  Yuma MURATA ,  Naoyuki KANAI ,  Akito NAKAGOME ,  Yoshinari IKEDA

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/07

Abstract: A semiconductor module includes a first semiconductor element and a second semiconductor element each having an upper-surface electrode and a lower-surface electrode, and being connected in parallel to configure an upper arm, a first conductive layer having a U-shape in planar view, having two end portions, and having an upper surface on which the first semiconductor element and the second semiconductor element are disposed in a mirror image arrangement, a positive electrode terminal having a body part and at least two positive electrode ends branched from the body part, and a negative electrode terminal having a negative electrode end disposed between the positive electrode ends. The positive electrode ends are respectively connected to one of the two end portions of the first conductive layer.

公开(公告)号：US20240006303A1

公开(公告)日：2024-01-04

申请号：US18469840

申请日：2023-09-19

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryoichi KATO ,  Yoshinari IKEDA ,  Yuma MURATA

IPC: H01L23/522 ,  H01L23/49 ,  H01L23/498 ,  H01L25/16 ,  H01R4/02 ,  H01R43/02

CPC classification number: H01L23/5222 ,  H01L23/49 ,  H01L23/49811 ,  H01L25/162 ,  H01R4/029 ,  H01R43/0221

Abstract: A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.

公开(公告)号：US20230187323A1

公开(公告)日：2023-06-15

申请号：US17975444

申请日：2022-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Shinji TADA ,  Yuma MURATA

IPC: H01L23/495 ,  H01L23/04 ,  H01L23/492 ,  H01L23/06 ,  H01L23/00

CPC classification number: H01L23/49537 ,  H01L23/04 ,  H01L23/06 ,  H01L23/492 ,  H01L24/09 ,  H01L2224/0903

Abstract: A semiconductor device, including a case that has a first power terminal including a first bonding area and a second power terminal including a second bonding area, and an insulating unit located between the first power terminal and the second power terminal, and having a shape of a flat plate, the insulating unit being bonded to the case. The insulating unit has a first insulating portion in a sheet form, and a second insulating portion which covers an upper surface, a lower surface, or both the upper and lower surfaces, of the first insulating portion. The first bonding area and the second bonding area are exposed from the insulating unit and from the case.

公开(公告)号：US20230142607A1

公开(公告)日：2023-05-11

申请号：US17956787

申请日：2022-09-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tadahiko SATO ,  Ryoichi KATO ,  Yuma MURATA

IPC: H01L23/498 ,  H01L21/48 ,  H01R12/55 ,  H01R4/02 ,  H01R43/02 ,  H01G2/06

CPC classification number: H01L23/49811 ,  H01G2/06 ,  H01L21/4853 ,  H01R4/029 ,  H01R12/55 ,  H01R43/0221 ,  H01L25/072

Abstract: A semiconductor module includes an insulating sheet which has a first surface and extends in a first direction and a first terminal. The first terminal has a first region disposed on the first surface of the insulating sheet and having a first width in a second direction perpendicular to the first direction, a second region extending from the first region and having a second width in the second direction narrower than the first width, and a third region located away from the first surface and being electrically connected to both the first region and the second region.

公开(公告)号：US20210280555A1

公开(公告)日：2021-09-09

申请号：US17185931

申请日：2021-02-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yuma MURATA ,  Ryoichi KATO ,  Naoyuki KANAI ,  Akito NAKAGOME ,  Yoshinari IKEDA

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/07

Abstract: A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.