Abstract:
A hybrid storage device includes a controller, a volatile storage unit, and a non-volatile storage unit. When the hybrid storage device is in a first working mode, the volatile storage unit is in an enabled state, and the non-volatile storage unit is in a disabled state; when the hybrid storage device is in a second working mode, the non-volatile storage unit is in an enabled state, and the volatile storage unit is in a disabled state. When the hybrid storage device runs in the first working mode, and when detecting that a running parameter of the computer meets a first switching condition, the controller enables the non-volatile storage unit, copies data in the volatile storage unit to the non-volatile storage unit, and switches the hybrid storage device to the second working mode.
Abstract:
A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.
Abstract:
A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.
Abstract:
An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.
Abstract:
The invention provides a resistive random access memory and a writing operation method thereof, and pertains to the technical field of resistive random access memory (ReRAM). The resistive random access memory comprises a writing operation signal generation module which is at least used for generating electrical signal(s) hazing gradually reducing voltages as set operation signals; in a Set operation method of the writing operation method, electrical signal(s) hazing gradually reducing voltages are biased, as Set operation signals, onto a selected memory unit in the resistive random access memory. The Set operation method can improve storage performances of ReRAM in terms of endurance, data retention and high resistance/low resistance window, etc.