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公开(公告)号：US06670655B2
公开(公告)日：2003-12-30
申请号：US09837839
申请日：2001-04-18
IPC分类号： H01L27148
CPC分类号： H01L27/1203 , H01L29/783
摘要： A method and apparatus are provided for implementing a body contact in a silicon-on-insulator field effect transistor device. A SOI field effect transistor is provided having a body contact having a predefined resistance that provides a higher device threshold voltage in the SOI FET device. A body of the SOI field effect transistor is connected to the gate of the SOI field effect transistor. The body gate connection of the SOI field effect transistor effectively lowers the device threshold voltage due to body bias effect. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor is used in circuits having stacked devices and DC currents. The SOI field effect transistor with a body connected to the gate of the SOI field effect transistor also is used in analog circuits with device matching requirements and in circuits having a low voltage power supply.
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2.发明授权Method and low voltage CMOS circuit for generating voltage and current references 失效用于产生电压和电流参考的方法和低压CMOS电路公开(公告)号：US06859092B2
公开(公告)日：2005-02-22
申请号：US10418569
申请日：2003-04-17
CPC分类号： G05F1/46
摘要： A method and a low voltage, complementary metal oxide semiconductor (CMOS) circuit are provided for generating voltage and current references with a low voltage power supply. A voltage generating circuit provides a voltage reference and is formed by a plurality of CMOS transistors and a resistor. An operational amplifier includes a differential pair of CMOS transistors. The first voltage reference is applied to an input of the differential pair of transistors and an output of the differential pair of transistors providing a second voltage reference. The operational amplifier includes a plurality of current reference transistors. A first voltage generating circuit generates a first voltage and a second voltage generating circuit generating a second voltage. The first and second voltage generating circuits are formed by a plurality of CMOS transistors. The generated first and second voltages are applied to the voltage reference generating circuit and current reference transistors.
摘要翻译： 提供一种方法和低电压互补金属氧化物半导体（CMOS）电路，用于利用低电压电源产生电压和电流参考。 电压产生电路提供电压参考，并由多个CMOS晶体管和电阻器形成。 运算放大器包括一对差分CMOS晶体管。 第一参考电压被施加到晶体管的差分对的输入和提供第二电压基准的晶体管的差分对的输出。 运算放大器包括多个电流参考晶体管。 第一电压产生电路产生产生第二电压的第一电压和第二电压产生电路。 第一和第二电压产生电路由多个CMOS晶体管形成。 产生的第一和第二电压被施加到电压参考产生电路和电流参考晶体管。
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3.发明授权Method and reference circuit for bias current switching for implementing an integrated temperature sensor 失效用于实现集成温度传感器的偏置电流开关的方法和参考电路公开(公告)号：US07118274B2
公开(公告)日：2006-10-10
申请号：US10849580
申请日：2004-05-20
CPC分类号： G01K7/01
摘要： A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.
摘要翻译： 提供了用于实现集成温度传感器的偏置电流切换的方法和参考电路。 产生第一偏置电流并且恒定地施加到热感测二极管。 通过选择性地将乘法电流从电流乘法器切换到热感测二极管或负载二极管，来向热感测二极管提供第二偏置电流。 参考电路包括耦合到电流镜的参考电流源。 电流镜向热敏二极管提供第一偏置电流。 电流镜耦合到提供倍增电流的电流倍增器。 到热敏二极管的第二偏置电流包括第一偏置电流和来自当前乘法器的相乘电流。 通过选择性地切换热感测二极管和虚拟负载二极管之间的倍增电流来提供到热敏二极管的第二偏置电流。
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公开(公告)号：US06724256B1
公开(公告)日：2004-04-20
申请号：US10289604
申请日：2002-11-07
IPC分类号： H03F345
CPC分类号： H03F3/45278 , H03F3/45085 , H03F2203/45646 , H03F2203/45652 , H03F2203/45722
摘要： A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.
摘要翻译： 接收机具有对输入幅度和转换速率通常不敏感的延迟。 接收器包括具有共同发射极连接的第一差分晶体管对。 差分输入被施加到差分晶体管对的相应基极。 一对负载晶体管连接到差分晶体管对的各个集电极。 相应的电阻耦合到负载晶体管的基极，用于提供独立于差分输入的延迟; 并且一对偏置晶体管耦合到差分晶体管对的相应集电极以偏置负载晶体管。
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公开(公告)号：US07173482B2
公开(公告)日：2007-02-06
申请号：US11094711
申请日：2005-03-30
IPC分类号： G05F1/10
CPC分类号： G05F3/242
摘要： A complementary metal oxide semiconductor (CMOS) voltage regulator for low headroom applications includes a differential input common mode range amplifier. The differential input common mode range amplifier is formed by a plurality of CMOS transistors. A source follower CMOS transistor is coupled to an output of the differential input common mode range amplifier for providing an output of the CMOS voltage regulator. A current source is coupled to the differential input common mode range amplifier for maintaining a bias current through the differential input common mode range amplifier.
摘要翻译： 用于低余量应用的互补金属氧化物半导体（CMOS）电压调节器包括差分输入共模范围放大器。 差分输入共模范围放大器由多个CMOS晶体管形成。 源极跟随器CMOS晶体管耦合到差分输入共模范围放大器的输出，用于提供CMOS电压调节器的输出。 电流源耦合到差分输入共模范围放大器，用于保持偏置电流通过差分输入共模范围放大器。
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公开(公告)号：US06693465B1
公开(公告)日：2004-02-17
申请号：US10345558
申请日：2003-01-16
IPC分类号： H03K522
CPC分类号： H03K5/2481 , H04L25/08
摘要： Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.
摘要翻译： 公开了用于检测增强型差分接收器上的开放输入的电路。 下拉终端器耦合到增强型差分接收器的输入端。 如果差分输入未被主动驱动，则两个差分输入端的电压将被拉至预定的电压。 当差分输入上的电压达到参考电压时，有源器件检测到已经达到参考电压，并且在增强差分接收器的输出上产生预定的逻辑值。 增强型差分接收器不主动驱动时不会发生振荡。 通过增强型差分接收器的延迟通过仅由差分放大器组成的常规差分接收器的延迟实质上不大。
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7.发明授权Optimizing performance of a clocked system by adjusting clock control settings and clock frequency 失效通过调整时钟控制设置和时钟频率来优化时钟系统的性能公开(公告)号：US06535986B1
公开(公告)日：2003-03-18
申请号：US09524878
申请日：2000-03-14
IPC分类号： G06F108
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.
摘要翻译： 公开了一种调节计时系统（如数字计算机或存储器控制器）的操作或定时裕度的方法。 该方法可以在每个初始程序加载时自动发生，或者可以针对频率，操作电压或其中定时裕度不那么关键的应用进行手动调整。 设置时钟的初始或默认频率。 诸如占空比，VCO范围和增益等的时钟控制设置也被初始化并设置为一些默认值。 在时钟系统上执行诸如ABIST，LBIST或其他功能测试的测试，并且时钟频率逐渐增加，直到测试失败。 测试失败后，调整一个或多个时钟控制设置，并在故障频率下再次运行测试。 如果测试成功完成，表明没有错误，则时钟频率再次递增，直到测试失败。 再次，时钟控制设置被调整，测试以增加的频率重复，直到测试失败或直到达到期望的时序余量。
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8.发明申请Phase Frequency Detector Circuit for Implementing Low PLL Phase Noise and Low Phase Error 审中-公开用于实现低PLL相位噪声和低相位误差的相位检波器电路公开(公告)号：US20090302904A1
公开(公告)日：2009-12-10
申请号：US12136218
申请日：2008-06-10
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03D13/004 , H03L7/093
摘要： A method and Phase Frequency Detector (PFD) circuit for implementing low phase locked loop (PLL) phase noise and low phase error, and a design structure on which the subject circuit resides are provided. The PFD circuit includes a PFD latch receiving clock and reset signals, and PFD output driver circuit providing PFD output signals. The PFD latch is set by the clock and reset by the reset signal. An AND gate coupled to the PFD latch and the PFD output driver circuit includes differential inputs and outputs and applies the reset signal to the PFD latch. The PFD latch, AND gate and PFD output driver circuit are formed by current mode logic using bipolar transistors. An active loop filter generates a tuning voltage output.
摘要翻译： 一种用于实现低锁相环（PLL）相位噪声和低相位误差的方法和相位频率检测器（PFD）电路，以及提供主题电路所在的设计结构。 PFD电路包括PFD锁存器接收时钟和复位信号，PFD输出驱动电路提供PFD输出信号。 PFD锁存器由时钟设置，并由复位信号复位。 耦合到PFD锁存器和PFD输出驱动器电路的与门包括差分输入和输出，并将复位信号施加到PFD锁存器。 PFD锁存器，与门和PFD输出驱动器电路由使用双极晶体管的电流模式逻辑形成。 有源环路滤波器产生调谐电压输出。
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