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    MOS(metal oxide silicon) controlled thyristor device
    1.
    发明授权
    MOS(metal oxide silicon) controlled thyristor device 有权

    公开(公告)号：US11784247B2

    公开(公告)日：2023-10-10

    申请号：US17792070

    申请日：2021-06-10

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kun Sik Park ,  Jong Il Won ,  Doo Hyung Cho ,  Dong Yun Jung ,  Hyun Gyu Jang

    IPC: H01L29/745 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    CPC classification number: H01L29/7455 ,  H01L29/0839 ,  H01L29/1012 ,  H01L29/66378

    Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

    Non-volatile memory (NVM) and method for manufacturing thereof
    2.
    发明授权
    Non-volatile memory (NVM) and method for manufacturing thereof 有权
    非易失性存储器（NVM）及其制造方法

    公开(公告)号：US09171621B2

    公开(公告)日：2015-10-27

    申请号：US13871300

    申请日：2013-04-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kun Sik Park ,  Kyu Ha Baek

    IPC: G11C16/04 ,  H01L29/788 ,  H01L29/66 ,  H01L27/115

    CPC classification number: G11C16/0425 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells. Further, the nonvolatile memory according to the exemplary embodiment may constantly maintain a voltage of a shared well region in the tunneling MOSFET and apply a different voltage to a source/drain from that of an adjacent cell, thereby recording data only in the selected memory cell or deleting recorded data from the selected memory cell while sharing the well region.

    Abstract translation: 公开了非易失性存储器和制造非易失性存储器的方法。 根据示例性实施例的非易失性存储器可以包括在衬底上形成的深阱，在深阱内形成的第一阱，与深阱内的第一阱分开形成的第二阱，第一金属氧化物半导体场 - 形成在第一阱上的效应晶体管（MOSFET）和形成在第二阱上的第二MOSFET。 根据根据示例性实施例的制造非易失性存储器的方法，存储器单元的控制MOSFET的阱区可以与相邻存储器单元的控制MOSFET或存储器的隧道MOSFET的阱区共享 单元可以与相邻存储器单元的隧道MOSFET共享，从而减小存储单元的面积。 此外，根据示例性实施例的非易失性存储器可以恒定地保持隧道MOSFET中的共享阱区的电压，并且向相邻单元的源极/漏极施加不同的电压，从而仅将数据记录在所选存储单元 或者在共享井区域的同时从所选存储单元中删除记录数据。

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