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公开(公告)号：US11784247B2
公开(公告)日：2023-10-10
申请号：US17792070
申请日：2021-06-10
Inventor： Kun Sik Park , Jong Il Won , Doo Hyung Cho , Dong Yun Jung , Hyun Gyu Jang
IPC: H01L29/745 , H01L29/08 , H01L29/10 , H01L29/66
CPC classification number: H01L29/7455 , H01L29/0839 , H01L29/1012 , H01L29/66378
Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.
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公开(公告)号：US09123548B1
公开(公告)日：2015-09-01
申请号：US14449028
申请日：2014-07-31
Inventor： Jin-Gun Koo , Jong Il Won , Hyun-cheol Bae , Sang Gi Kim , Yil Suk Yang
IPC: H01L29/06 , H01L29/10 , H01L21/8249
CPC classification number: H01L29/0634 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0657 , H01L29/1095 , H01L29/41741 , H01L29/6625 , H01L29/735 , H01L29/7813 , H01L29/7835
Abstract: Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.
Abstract translation: 提供一种半导体器件。 该半导体器件包括：第一半导体层，其具有带有第一器件的第一区域和具有第二器件的第二区域; 设置在所述第一半导体层中并将所述第一装置和所述第二装置彼此电分离的装置隔离图案; 设置在所述第一半导体层的所述第一区域的下表面上的漏极; 以及设置在所述第一半导体层的所述第二区域的下表面上的第二半导体层。
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公开(公告)号：US11637192B2
公开(公告)日：2023-04-25
申请号：US17355977
申请日：2021-06-23
Inventor： Kun Sik Park , Jong Il Won , Doo Hyung Cho , Hyun Gyu Jang , Dong Yun Jung
IPC: H01L29/749 , H01L29/745 , H01L29/66
Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
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