公开(公告)号：US20110272779A1

公开(公告)日：2011-11-10

申请号：US13189016

申请日：2011-07-22

申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

公开(公告)号：US07943493B2

公开(公告)日：2011-05-17

申请号：US12873882

申请日：2010-09-01

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/20

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US20100330783A1

公开(公告)日：2010-12-30

申请号：US12873882

申请日：2010-09-01

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/20

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US20090135640A1

公开(公告)日：2009-05-28

申请号：US11946450

申请日：2007-11-28

申请人： Deok-Kee Kim ,  Chuck Thuc Le ,  Byeongju Park

发明人： Deok-Kee Kim ,  Chuck Thuc Le ,  Byeongju Park

IPC分类号： G11C17/16

CPC分类号： G11C17/16

摘要： An electromigration-programmable semiconductor device may be programmed to increase the resistance or to decrease the resistance by selecting the amount of current passed through the electromigration-programmable semiconductor device. The electromigration-programmable semiconductor device comprises an anode, a cathode, and a link, each having a semiconductor portion and a metal semiconductor alloy portion. The metal semiconductor alloy portion of the link comprises two disjoined sub-portions with a gap therebetween. A low programming current fills the gap by electromigrating a small amount of metal semiconductor alloy from the cathode, A high programming current forms a large metal-semiconductor-alloy-deleted area in the cathode to increase the resistance. A tri-state programming is achieved by selecting the programming current level.

摘要翻译： 可以编程电迁移可编程半导体器件以通过选择通过电迁移可编程半导体器件的电流量来增加电阻或降低电阻。 电迁移可编程半导体器件包括阳极，阴极和链路，每个具有半导体部分和金属半导体合金部分。 连接件的金属半导体合金部分包括两个在它们之间具有间隙的分离的子部分。 低编程电流通过从阴极电解少量金属半导体合金来填充间隙。高编程电流在阴极中形成大的金属 - 半导体 - 合金缺失区域以增加电阻。 通过选择编程电流电平实现三态编程。

公开(公告)号：US20090090993A1

公开(公告)日：2009-04-09

申请号：US11867268

申请日：2007-10-04

申请人： William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

发明人： William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting terminal structures. “Undercutting” techniques are employed whereby a structure is formed atop a buried layer, and that buried layer is removed by selective etching. Whereby a “floating” silicide eFUSE conductor is formed on a silicon beam structure. In its initial state, the eFUSE silicide is highly conductive, exhibiting low electrical resistance (the “unblown state of the eFUSE). When a sufficiently large current is passed through the eFUSE conductor, localized heating occurs. This heating causes electromigration of the silicide into the silicon beam (and into surrounding silicon, thereby diffusing the silicide and greatly increasing its electrical resistance. When the current source is removed, the silicide remains permanently in this diffused state, the “blown” state of the eFUSE.

摘要翻译： 通过在空气中形成硅“浮动光束”形成集成eFUSE装置，于是eFUSE装置的可熔部分驻留。 该梁在两个更大的支撑端子结构之间延伸。 采用“底切”技术，由此在掩埋层顶部形成结构，并且通过选择性蚀刻去除掩埋层。 由此在硅梁结构上形成“浮动”硅化物eFUSE导体。 在初始状态下，eFUSE硅化物具有高导电性，表现出较低的电阻（eFUSE的未吹出状态），当足够大的电流通过eFUSE导体时，发生局部加热，该加热导致硅化物的电迁移 （并且进入周围的硅，从而扩散硅化物并大大增加其电阻。当电流源被去除时，硅化物永久地保持在这种扩散状态，eFUSE的“吹”状态。

公开(公告)号：US08829645B2

公开(公告)日：2014-09-09

申请号：US12137640

申请日：2008-06-12

申请人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

发明人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.

摘要翻译： 电熔丝结构和方法具有阳极; 熔丝连接（熔丝连接的第一端连接到阳极）; 阴极（与第一端相对的熔断体的第二端连接到阴极）; 和熔丝链上的硅化物层。 硅化物层具有邻近阳极的第一硅化物区域和与阴极相邻的第二硅化物区域。 第二硅化物区域包括不包含在第一硅化物区域内的杂质。 此外，第一硅化物区域比第二硅化物区域薄。

公开(公告)号：US08574975B2

公开(公告)日：2013-11-05

申请号：US13785543

申请日：2013-03-05

申请人： Deok-Kee Kim

发明人： Deok-Kee Kim

IPC分类号： H01L21/8238

CPC分类号： H01L23/5382 ,  H01L21/28273 ,  H01L23/5252 ,  H01L23/5256 ,  H01L23/544 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7848 ,  H01L29/788 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: an e-fuse gate, a floating pattern between the e-fuse gate and an e-fuse active portion, a blocking dielectric pattern between the floating pattern and the e-fuse gate, and an e-fuse dielectric layer between the floating pattern and the e-fuse active portion. The floating pattern includes a first portion between the e-fuse gate and the e-fuse active portion and a pair of second portions extended upward along both sidewalls of the e-fuse gate from both edges of the first portion.

摘要翻译： 半导体器件包括：e熔丝栅极，e熔丝栅极和e-fuse有源部分之间的浮动图案，浮置图案和e-fuse栅极之间的阻挡介质图案，以及e熔丝电介质层 在浮动图案和e-保险丝活动部分之间。 浮动图案包括在e熔丝栅极和e-熔丝有源部分之间的第一部分和从第一部分的两个边缘沿着e-熔丝栅极的两个侧壁向上延伸的一对第二部分。

公开(公告)号：US07777297B2

公开(公告)日：2010-08-17

申请号：US11693041

申请日：2007-03-29

申请人： Haining S. Yang ,  Wai-Kin Li ,  Deok-Kee Kim

发明人： Haining S. Yang ,  Wai-Kin Li ,  Deok-Kee Kim

IPC分类号： H01L29/41

CPC分类号： H01L23/5256 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer.

摘要翻译： 熔丝结构包括通常位于衬底内并且复制衬底内的形貌特征的非平面熔断体材料层。 非平面熔断体材料层包括有助于在非平面熔断体材料层内提供较低切断电流的角弯曲。

公开(公告)号：US07732893B2

公开(公告)日：2010-06-08

申请号：US11683071

申请日：2007-03-07

申请人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

发明人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

IPC分类号： H01L29/04 ,  H01L31/036

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.

摘要翻译： 本发明提供一种用于实现具有更高电阻值的后编程电阻分布并提高电熔丝编程的可靠性的电熔丝结构。 公开了在阴极中与掺杂了P掺杂的半导体材料结合在阴极中的未掺杂半导体材料的部分掺杂的电熔丝结构，并且示出了所公开的电熔丝的优异性能的数据。

公开(公告)号：US07713792B2

公开(公告)日：2010-05-11

申请号：US11870007

申请日：2007-10-10

申请人： Anil Kumar Chinthakindi ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

发明人： Anil Kumar Chinthakindi ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

IPC分类号： H01L21/02 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.

摘要翻译： 熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。 至少部分单晶半导体材料层通过间隙与衬底分离。 单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。