公开(公告)号：US07923810B2

公开(公告)日：2011-04-12

申请号：US12288280

申请日：2008-10-17

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L21/70

CPC分类号： H01L27/0629 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635

摘要： A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element hole on the second exposed portion of the semiconductor region. A surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate may have a same conductivity type. Related methods are also discussed.

摘要翻译： 半导体器件可以包括半导体衬底的半导体区域，其中在半导体区域和半导体衬底的主体之间限定P-N结。 半导体衬底中的绝缘隔离结构可以围绕半导体区域的侧壁。 层间绝缘层可以在半导体衬底上，半导体区域上和绝缘隔离结构上，并且层间绝缘层可以具有暴露半导体区域的相应第一和第二部分的第一和第二间隔开的元件孔。 第一半导体图案可以在半导体区域的第一暴露部分上的第一元件孔中，并且第二半导体图案可以位于半导体区域的第二暴露部分上的第二元件孔中。 与半导体衬底相对的第一半导体图案的表面部分和与半导体衬底相对的第二半导体图案的表面部分可以具有相同的导电类型。 还讨论了相关方法。

公开(公告)号：US20090102012A1

公开(公告)日：2009-04-23

申请号：US12288280

申请日：2008-10-17

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L27/082

CPC分类号： H01L27/0629 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635

摘要： A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element;hole on the second exposed portion of the semiconductor region. A surface portion of the first semiconductor pattern opposite the semiconductor substrate and a surface portion of the second semiconductor pattern opposite the semiconductor substrate may have a same conductivity type. Related methods are also discussed.

摘要翻译： 半导体器件可以包括半导体衬底的半导体区域，其中在半导体区域和半导体衬底的主体之间限定P-N结。 半导体衬底中的绝缘隔离结构可以围绕半导体区域的侧壁。 层间绝缘层可以在半导体衬底上，半导体区域上和绝缘隔离结构上，并且层间绝缘层可以具有暴露半导体区域的相应第一和第二部分的第一和第二间隔开的元件孔。 第一半导体图案可以位于半导体区域的第一暴露部分的第一元件孔中，并且第二半导体图案可以在第二元件中;半导体区域的第二暴露部分上的孔。 与半导体衬底相对的第一半导体图案的表面部分和与半导体衬底相对的第二半导体图案的表面部分可以具有相同的导电类型。 还讨论了相关方法。

公开(公告)号：US20090098703A1

公开(公告)日：2009-04-16

申请号：US12248470

申请日：2008-10-09

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L21/20

CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

公开(公告)号：US20110084361A1

公开(公告)日：2011-04-14

申请号：US12973253

申请日：2010-12-20

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L27/06

CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

公开(公告)号：US08143674B2

公开(公告)日：2012-03-27

申请号：US12973253

申请日：2010-12-20

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L23/62

CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

公开(公告)号：US07871890B2

公开(公告)日：2011-01-18

申请号：US12248470

申请日：2008-10-09

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L21/20

CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

公开(公告)号：US20090285008A1

公开(公告)日：2009-11-19

申请号：US12419934

申请日：2009-04-07

申请人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

发明人： Hong-Sik Jeong ,  Kwang-Jin Lee ,  Dae-Won Ha ,  Gi-Tae Jeong ,  Jung-Hyuk Lee

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3459 ,  G11C2013/0076

摘要： A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles. Selectively pre-write verifying and writing of the received write data may include, for example, writing received write data to the selected memory cell region without pre-write verification responsive to the monitored number of read cycles being greater than a predetermined number of read cycles

摘要翻译： 监视应用于诸如可变电阻存储器件的存储器件的选定存储器位置的多个读周期。 接收要写入所选存储单元的写入数据。 基于所监视的读取周期数，对接收的写入数据进行选择性的预写入验证和写入。 选择性地预写入验证和写入所接收的写入数据可以包括例如将接收到的写入数据写入所选择的存储器单元区域，而无需预写入验证，响应于所监视的读取周期数大于预定数量的读取周期

公开(公告)号：US08451656B2

公开(公告)日：2013-05-28

申请号：US13487463

申请日：2012-06-04

申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

IPC分类号： G11C11/00

CPC分类号： G11C11/5678 ,  G11C11/56 ,  G11C13/0004

摘要： The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.

公开(公告)号：US08036018B2

公开(公告)日：2011-10-11

申请号：US12917175

申请日：2010-11-01

申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/00 ,  G11C5/06

CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

公开(公告)号：US07804703B2

公开(公告)日：2010-09-28

申请号：US12120583

申请日：2008-05-14

申请人： Dae-Won Ha ,  Gi-Tae Jeong

发明人： Dae-Won Ha ,  Gi-Tae Jeong

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

摘要翻译： 相变存储器件包括沿着半导体衬底上的方向延伸的字线。 低浓度半导体图案设置在字线上。 节点电极设置在低浓度半导体图案上。 肖特基二极管设置在低浓度半导体图案和节点电极之间。 相变电阻器设置在节点电极上。