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    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09214526B2

    公开(公告)日：2015-12-15

    申请号：US14557662

    申请日：2014-12-02

    申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

    发明人： Hidefumi Takaya ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

    IPC分类号： H01L29/78 ,  H01L29/423

    CPC分类号： H01L29/4236 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

    摘要： A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.

    摘要翻译： 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型的主体层; 具有第一导电类型的第一半导体区; 栅极绝缘膜; 沟槽栅电极; 第一主电极; 具有第二导电类型的第二半导体区; 和导体区域。 第一主电极与主体层和第一半导体区电连接。 第二半导体区域设置在栅极沟槽的底部，被漂移层包围。 导体区域被配置为将第一主电极与第二半导体区域电连接，并且被配置为当半导体器件处于截止状态时使第二半导体区域的电位和第一主电极的电位相等。

    Silicon carbide semiconductor device
    4.
    发明授权
    Silicon carbide semiconductor device 有权

    公开(公告)号：US10714611B2

    公开(公告)日：2020-07-14

    申请号：US16505760

    申请日：2019-07-09

    申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

    发明人： Yuichi Takeuchi ,  Atsuya Akiba ,  Sachiko Aoi ,  Katsumi Suzuki

    IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/04 ,  H01L29/04 ,  H01L29/739

    摘要： A silicon carbide semiconductor device includes: a vertical semiconductor element, which includes: a semiconductor substrate made of silicon carbide and having a high impurity concentration layer on a back side and a drift layer on a front side; a base region made of silicon carbide on the drift layer; a source region arranged on the base region and made of silicon carbide; a deep layer disposed deeper than the base region; a trench gate structure including a gate insulation film arranged on an inner wall of a gate trench which is arranged deeper than the base region and shallower than the deep layer, and a gate electrode disposed on the gate insulation film; a source electrode electrically connected to the base region, the source region, and the deep layer; and a drain electrode electrically connected to the high impurity concentration layer.

    Field effect transistor incorporating a Schottky diode
    6.
    发明授权
    Field effect transistor incorporating a Schottky diode 有权
    掺入肖特基二极管的场效应晶体管

    公开(公告)号：US09391190B2

    公开(公告)日：2016-07-12

    申请号：US14299922

    申请日：2014-06-09

    申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

    发明人： Yukihiko Watanabe ,  Sachiko Aoi ,  Hidefumi Takaya ,  Atsuya Akiba

    IPC分类号： H01L29/78 ,  H01L29/872 ,  H01L29/66 ,  H01L27/02 ,  H01L21/04 ,  H01L29/16

    CPC分类号： H01L29/7806 ,  H01L21/049 ,  H01L21/0495 ,  H01L27/0255 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/872

    摘要： A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.

    摘要翻译： 结合肖特基二极管的FET具有能够自由调节形成肖特基二极管的区域与形成FET的区域的比例的结构。 利用长距离延伸的沟槽。 肖特基电极插入在沟槽的纵向上间断地出现的位置。 通过利用在SiC上形成的热氧化膜的生长速度较慢，并且在多晶硅上形成的热氧化膜的生长速度更快，可以获得在栅电极和肖特基电极之间形成绝缘膜的结构 在栅电极和源极区之间，栅电极与体区之间以及栅电极和漏区之间，并且在肖特基电极和漏极区之间不形成绝缘膜。

    SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    SCHOTTKY BARRIER DIODE AND METHOD FOR MANUFACTURING THE SAME 有权
    肖特彼勒二极管及其制造方法

    公开(公告)号：US20160181355A1

    公开(公告)日：2016-06-23

    申请号：US14975961

    申请日：2015-12-21

    申请人： Toyota Jidosha Kabushiki Kaisha ,  Denso Corporation

    发明人： Tatsuji Nagaoka ,  Hiroki Miyake ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

    IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/16 ,  H01L29/872

    CPC分类号： H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/66143 ,  H01L29/872

    摘要： A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

    摘要翻译： 本文提供的肖特基势垒二极管包括：半导体衬底; 以及与半导体衬底接触的阳极电极。 半导体衬底包括：与阳极电极接触的p型接触区域; 以及在没有设置p型接触区域的范围内通过肖特基接触与阳极电极接触的n型漂移区域p型接触区域包括：多个圆形区域，其位于圆形区域 在所述半导体衬底和所述阳极电极之间的接触表面处间隔布置在所述外侧和内侧之间; 以及位于位于接触表面的最内侧的圆形区域的内部的内部区域，并且连接到位于接触表面最内侧的圆形区域。

    Compound semiconductor device and method for manufacturing the same
    9.
    发明授权
    Compound semiconductor device and method for manufacturing the same 有权

    公开(公告)号：US10593750B2

    公开(公告)日：2020-03-17

    申请号：US16069914

    申请日：2017-01-19

    申请人： DENSO CORPORATION

    发明人： Yuichi Takeuchi ,  Atsuya Akiba ,  Katsumi Suzuki ,  Yusuke Yamashita

    IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

    摘要： A method for manufacturing a compound semiconductor device includes: providing a semiconductor substrate including a foundation layer having a first conductivity type; forming a deep trench in the foundation layer; and forming a deep layer having a second conductivity type by introducing material gas of the compound semiconductor while introducing dopant gas into an epitaxial growth equipment to cause epitaxial growth of the deep layer in the deep trench. A period in which a temperature in the epitaxial growth equipment is increased to a temperature of the epitaxial growth of the deep layer is defined as a temperature increasing period. In the forming the deep layer, the deep layer is further formed in a bottom corner portion of the deep trench by starting the introducing of the dopant gas during the temperature increasing period and starting the introducing of the material gas after the temperature increasing period.