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公开(公告)号：US07180349B2
公开(公告)日：2007-02-20
申请号：US11244547
申请日：2005-10-06
申请人： Curtis R. Leifso , Samuel A. Tiller
发明人： Curtis R. Leifso , Samuel A. Tiller
IPC分类号： H03K3/12
CPC分类号： H03K23/544
摘要： A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.
摘要翻译： 一种分频器电路，用于提供具有小于输入系统时钟信号的频率的奇整数因子的频率的分频时钟信号。 该分频器包括一个时钟发生器电路，该时钟发生器电路耦合到延迟电路，该延迟电路工作在有效和复位阶段，以提供来自系统时钟信号的分频时钟信号。 在有源相位中，时钟发生器电路将分频时钟信号驱动到第一逻辑状态直到接收到复位信号。 然后，在分频时钟信号被驱动到第一逻辑状态之后，延迟电路在预定数量的系统时钟边沿产生复位信号。 在复位阶段，响应于复位信号复位时钟发生器电路和延迟电路，使得时钟发生器电路立即将分频时钟信号驱动到第二逻辑状态，并且延迟电路使得复位信号在 预定数量的系统时钟边沿。 延迟电路为分频时钟信号保持50％的占空比。
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公开(公告)号：US06992513B2
公开(公告)日：2006-01-31
申请号：US10985238
申请日：2004-11-10
申请人： Curtis R. Leifso , Samuel A. Tiller
发明人： Curtis R. Leifso , Samuel A. Tiller
IPC分类号： H03B19/00
CPC分类号： H03K23/544
摘要： A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.
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3.发明授权System and method of amplifier gain control by variable bias and degeneration 有权放大器增益控制的系统和方法，通过可变偏置和退化公开(公告)号：US06870425B2
公开(公告)日：2005-03-22
申请号：US10414780
申请日：2003-04-16
申请人： Curtis R. Leifso , Samuel A. Tiller
发明人： Curtis R. Leifso , Samuel A. Tiller
CPC分类号： H03F3/45085 , H03F3/45179 , H03F2203/45292 , H03F2203/45454 , H03F2203/45626 , H03F2203/45691 , H03F2203/45702 , H03G1/0023
摘要： A gain control circuit that permits a variable gain amplifier circuit to operate with high input linearity and low power consumption is disclosed. The variable gain amplifier includes a standard differential bipolar transistor input circuit and a pair of degeneration transistors connected to a current source transistor. The gain control circuit provides a variable degeneration control voltage to vary the effective resistance of the degeneration transistors and a variable bias voltage to vary the current of the current source transistor. The input linearity of the variable gain amplifier is controlled independently of gain by adjusting the effective resistance and the current in an inverse relationship such that at maximum gain the current is at a maximum while the degeneration resistance is at a minimum, and at minimum gain the current is at a minimum while the degeneration resistance is at a maximum. Therefore the variable gain amplifier can be controlled to operate with high input linearity and low power at lower ranges of gain.
摘要翻译： 公开了一种允许可变增益放大器电路以高输入线性度和低功耗运行的增益控制电路。 可变增益放大器包括标准差分双极晶体管输入电路和连接到电流源晶体管的一对退化晶体管。 增益控制电路提供可变退化控制电压以改变退化晶体管的有效电阻和可变偏置电压以改变电流源晶体管的电流。 可变增益放大器的输入线性度通过调整有效电阻和电流成反比关系而独立于增益来控制，使得在最大增益时电流处于最大值，而退化电阻最小，而最小增益 电流最小，而退化电阻最大。 因此，可以控制可变增益放大器在较低的增益范围内以高输入线性度和低功耗运行。
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公开(公告)号：US06847239B2
公开(公告)日：2005-01-25
申请号：US10414876
申请日：2003-04-16
申请人： Curtis R. Leifso , Samuel A. Tiller
发明人： Curtis R. Leifso , Samuel A. Tiller
CPC分类号： H03K23/544
摘要： A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.
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公开(公告)号：US5365138A
公开(公告)日：1994-11-15
申请号：US160628
申请日：1993-12-02
CPC分类号： H03H9/6463 , H03H9/0057 , H03H9/25
摘要： A double mode surface wave resonator comprises two IDTs (inter-digital transducers), arranged side by side between reflection gratings, on a surface of a piezoelectric substrate to provide for coupling of surface waves therebetween, each IDT having interleaved electrodes extending from a common rail between the two IDTs and from a respective outer rail of the IDT. One or each of the IDTs and its outer rail is divided into two halves for providing a differential signal connection to the resonator. The electrodes of the IDTs can be arranged in spatial synchronism with adjacent fingers of the reflection gratings to reduce spurious longitudinal modes.
摘要翻译： 双模表面波谐振器包括在压电基板的表面上并排布置在反射光栅之间的两个IDT（数字间换能器），以提供其间的表面波的耦合，每个IDT具有从共轨延伸的交错电极 在两个IDT之间和IDT的相应外轨之间。 一个或每个IDT及其外轨被分成两半，用于提供与谐振器的差分信号连接。 IDT的电极可以与反射光栅的相邻指状物以空间同步的方式布置，以减少杂散的纵向模式。
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公开(公告)号：US5896062A
公开(公告)日：1999-04-20
申请号：US822460
申请日：1997-03-21
申请人： Samuel A. Tiller , Stephen G. Roy
发明人： Samuel A. Tiller , Stephen G. Roy
CPC分类号： H03F3/72 , H03F2200/294 , H03F2200/372
摘要： In an amplifier circuit, bias feedback to an amplifying transistor is provided by interconnecting the DC bias voltage applied to the transistor output and the transistor input with a feedback circuit consisting of a switching transistor and bias resistors. Bias current and stable operation is provided by this design. In a particular embodiment two common emitter amplifying transistors are connected to a common output and each has a separate bias feedback circuit including a respective switching transistor. A single DC control input connected to the inputs of both switching transistors can be used to switch between the two amplifying transistors depending on the value of the control voltage thereby amplifying either an input signal of the first amplifying transistor or an input signal of the second amplifying transistor.
摘要翻译： 在放大器电路中，通过将施加到晶体管输出的直流偏压和晶体管输入与由开关晶体管和偏置电阻组成的反馈电路互连，来提供对放大晶体管的偏置反馈。 本设计提供了偏置电流和稳定运行。 在特定实施例中，两个公共发射极放大晶体管连接到公共输出，并且每个具有包括相应开关晶体管的单独的偏置反馈电路。 连接到两个开关晶体管的输入的单个DC控制输入可以用于根据控制电压的值在两个放大晶体管之间切换，从而放大第一放大晶体管的输入信号或第二放大晶体管的输入信号 晶体管。
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公开(公告)号：US06897734B2
公开(公告)日：2005-05-24
申请号：US10691986
申请日：2003-10-23
申请人： Samuel A. Tiller
发明人： Samuel A. Tiller
CPC分类号： H03D7/1433 , H03B5/1209 , H03B5/1231 , H03D7/1441 , H03D7/1458 , H03D2200/009
摘要： A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filer network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.
摘要翻译： 本文公开了一种用于提供振荡器和混频器的功能的装置。 该装置使用差分对来为第一和第二滤波器网络提供时变信号。 第一个滤波器网络通过使用产生的负电阻产生振荡信号，并提供振荡信号，同时滤除不需要的信号。 第二滤波器网络接收时变输入信号和振荡信号，并提供混合输出，同时防止在振荡信号频率下的振荡传输。 还公开了双重平衡的实施例。
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公开(公告)号：US06864754B2
公开(公告)日：2005-03-08
申请号：US10254332
申请日：2002-09-25
申请人： Samuel A. Tiller
发明人： Samuel A. Tiller
CPC分类号： H03D7/1433 , H03B5/1209 , H03B5/1231 , H03D7/1441 , H03D7/1458 , H03D2200/009
摘要： A device for providing the functionality of an oscillator and mixer is disclosed herein. The device uses a differential pair to provide first and second filter networks with a time varying signal. The first filter network generates an oscillating signal through the use of a generated negative resistance and provides the oscillating signal while filtering out unwanted signals. The second filter network receives the time varying input signal and the oscillating signal and provides a mixed output while preventing the transmission of oscillations at the oscillating signal frequency. A double balanced embodiment is also disclosed.
摘要翻译： 本文公开了一种用于提供振荡器和混频器的功能的装置。 该装置使用差分对来为第一和第二滤波器网络提供时变信号。 第一个滤波器网络通过使用产生的负电阻产生振荡信号，并提供振荡信号，同时滤除不需要的信号。 第二滤波器网络接收时变输入信号和振荡信号，并提供混合输出，同时防止在振荡信号频率下的振荡传输。 还公开了双重平衡的实施例。
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