- 专利标题: Frequency divider system
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申请号: US10985238申请日: 2004-11-10
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公开(公告)号: US06992513B2公开(公告)日: 2006-01-31
- 发明人: Curtis R. Leifso , Samuel A. Tiller
- 申请人: Curtis R. Leifso , Samuel A. Tiller
- 申请人地址: CA Waterloo
- 专利权人: Research In Motion Limited
- 当前专利权人: Research In Motion Limited
- 当前专利权人地址: CA Waterloo
- 代理商 Jones Day; Krishna K. Pathiyal; Robert C. Liang
- 主分类号: H03B19/00
- IPC分类号: H03B19/00
摘要:
A frequency divider circuit for providing a divided clock signal having a frequency that is an odd integer factor less than the frequency of an incoming system clock signal. The frequency divider includes a clock generator circuit coupled to a delay circuit which operates in an active and a reset phase to provide a divided clock signal from the system clock signal. In the active phase, the clock generator circuit drives the divided clock signal to a first logic state until a reset signal is received. The delay circuit then generates the reset signal at a predetermined number of system clock edges after the divided clock signal is driven to the first logic state. In the reset phase, both the clock generator circuit and the delay circuit are reset in response to the reset signal such that the clock generator circuit immediately drives the divided clock signal to a second logic state, and the delay circuit disables the reset signal within the predetermined number of system clock edges. The delay circuit maintains a 50% duty cycle for the divided clock signal.
公开/授权文献
- US20050127959A1 Frequency divider system 公开/授权日:2005-06-16
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