公开(公告)号：US20130105859A1

公开(公告)日：2013-05-02

申请号：US13582432

申请日：2011-11-28

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，形成在衬底上的绝缘隔离层，形成在绝缘隔离层中的第一有源区和第二有源区，其特征在于，第一有源区 区域层和/或第二有源区层比衬底高。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区，增加沟道区中的载流子迁移率，从而显着改善器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US09419095B2

公开(公告)日：2016-08-16

申请号：US14119864

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/338 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US20120319215A1

公开(公告)日：2012-12-20

申请号：US13497744

申请日：2011-11-29

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/66651 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device and method of manufacturing the same, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; and forming a semiconductor device structure in and above the active region layer, wherein the carrier mobility of the active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, in the present invention a STI is formed first, and then filling is performed to form an active region, to avoid the problem of generation of holes in the STI and improve the device reliability.

Abstract translation: 本发明公开了一种半导体器件及其制造方法，包括：在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 以及在所述有源区域层中和之上形成半导体器件结构，其中所述有源区域层的载流子迁移率高于所述衬底的载流子迁移率。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区域，增加沟道区域中的载流子迁移率，从而显着提高器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，在本发明中，首先形成STI，然后进行填充以形成有源区，以避免在STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20120252225A1

公开(公告)日：2012-10-04

申请号：US13140549

申请日：2011-04-11

Applicant: Chunlong Li ,  Junfeng Li

Inventor： Chunlong Li ,  Junfeng Li

IPC: H01L21/316 ,  B82Y40/00

CPC classification number: H01L21/02238

Abstract: A semiconductor fabrication method is provided, in which a protective layer is deposited on the dummy wafer such that the protective layer fully encases the dummy wafer. Therefore, the dummy wafer will not be oxidized during thermal oxidation, thereby reducing dummy wafer consumption, decreasing production cost, avoiding particulate matter produced due to oxidation of the dummy wafer, and preventing the wafer to be oxidized from contamination.

Abstract translation: 提供一种半导体制造方法，其中保护层沉积在伪晶片上，使得保护层完全包住虚设晶片。 因此，在热氧化期间，伪晶片不会被氧化，从而减少了虚设晶片消耗，降低了生产成本，避免了由于虚设晶片的氧化而产生的颗粒物质，并且防止晶片被污染而被氧化。

公开(公告)号：US09202890B2

公开(公告)日：2015-12-01

申请号：US14119862

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L21/8249 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28123 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

Abstract translation: 提供了一种在门最后工艺中制造虚拟栅极的方法。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。 相应地，还提供了最后进程中的虚拟门。

公开(公告)号：US20120171833A1

公开(公告)日：2012-07-05

申请号：US13201109

申请日：2011-03-03

Applicant: Huilong Zhu ,  Chunlong Li ,  Jun Luo

Inventor： Huilong Zhu ,  Chunlong Li ,  Jun Luo

IPC: H01L29/78

CPC classification number: H01L29/66795

Abstract: The present application discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate, a gate stack and a second protection layer in sequence on a first insulating layer; after defining a gate region and removing portions of the second protection layer and the gate stack outside the gate region, while keeping portions of the stop layer, the semiconductor layer and the second insulating layer which covers sidewalls of the patterned semiconductor layer outside the gate region and exposing the sacrificial layer, performing source/drain ion implementation in the semiconductor layer; after forming a second sidewall spacer so as to cover at least the exposed portion of the sacrificial layer, removing the first protection layer and the second protection layer so as to expose the semiconductor layer and the gate stack; and forming a contact layer on the exposed portion of the semiconductor layer and the gate stack; performing planarization so as to expose the first protection layer, and then removing the first protection layer, the sacrificial layer, the stop layer and the semiconductor layer with the first sidewall spacer and the second sidewall spacer as a mask, so as to form a cavity which exposes the first insulating layer. It facilitates reduction of short channel effects, resistance of source/drain regions, and parasite capacitance.

Abstract translation: 本申请公开了一种用于制造半导体器件的方法，包括以下步骤：在第一绝缘层上依次形成半导体衬底，栅极堆叠和第二保护层; 在限定栅极区域并且在栅极区域外部去除第二保护层和栅极堆叠的部分之后，同时将覆盖图案化半导体层的侧壁的半导体层，半导体层和第二绝缘层的部分保持在栅极区域外部 并暴露所述牺牲层，在所述半导体层中执行源/漏离子实现; 在形成第二侧壁间隔物以至少覆盖牺牲层的暴露部分之后，去除第一保护层和第二保护层以露出半导体层和栅极堆叠; 以及在所述半导体层和所述栅叠层的暴露部分上形成接触层; 进行平面化以使第一保护层露出，然后用第一侧壁间隔件和第二侧壁间隔件作为掩模去除第一保护层，牺牲层，停止层和半导体层，以形成空腔 其暴露第一绝缘层。 它有助于减少短沟道效应，源/漏区电阻和寄生电容。

公开(公告)号：US20150035087A1

公开(公告)日：2015-02-05

申请号：US14119864

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/518

Abstract: A method for manufacturing a dummy gate in a gate-last process and a dummy gate in a gate-last process are provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines on the hard mask layer, and trimming the formed photoresist lines so that the trimmed photoresist lines a width less than or equal to 22 nm; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the trimmed photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer amorphous silicon.

Abstract translation: 提供了一种在门最后处理中制造伪栅极的方法和在栅极最后工艺中的伪栅极。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成光致抗蚀剂线，并修整所形成的光致抗蚀剂线，使得修整的光致抗蚀剂线的宽度小于或等于22nm; 并根据修整的光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层无定形 硅。

公开(公告)号：US20140332958A1

公开(公告)日：2014-11-13

申请号：US14119862

申请日：2012-12-12

Applicant: Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

Inventor： Chunlong Li ,  Junfeng Li ,  Jiang Yan ,  Chao Zhao

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28123 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for manufacturing a dummy gate in a gate-last process is provided. The method includes: providing a semiconductor substrate; growing a gate oxide layer on the semiconductor substrate; depositing bottom-layer amorphous silicon on the gate oxide layer; depositing an ONO structured hard mask on the bottom-layer amorphous silicon; depositing top-layer amorphous silicon on the ONO structured hard mask; depositing a hard mask layer on the top-layer amorphous silicon; forming photoresist lines having a width ranging from 32 nm to 45 nm on the hard mask layer; and etching the hard mask layer, the top-layer amorphous silicon, the ONO structured hard mask and the bottom-layer amorphous silicon in accordance with the photoresist lines, and removing the photoresist lines, the hard mask layer and the top-layer α-Si. Correspondingly, a dummy gate in a gate-last process is also provided.

Abstract translation: 提供了一种在门最后工艺中制造虚拟栅极的方法。 该方法包括：提供半导体衬底; 在半导体衬底上生长栅极氧化层; 在栅极氧化物层上沉积底层非晶硅; 在底层非晶硅上沉积ONO结构的硬掩模; 在ONO结构化的硬掩模上沉积顶层非晶硅; 在顶层非晶硅上沉积硬掩模层; 在硬掩模层上形成宽度范围为32nm至45nm的光致抗蚀剂线; 根据光致抗蚀剂线蚀刻硬掩模层，顶层非晶硅，ONO结构的硬掩模和底层非晶硅，并除去光致抗蚀剂线，硬掩模层和顶层α- Si。 相应地，还提供了最后进程中的虚拟门。

公开(公告)号：US08703567B2

公开(公告)日：2014-04-22

申请号：US13497744

申请日：2011-11-29

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/66651 ,  H01L29/7833

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming an insulating isolation layer on a substrate; forming an insulating isolation layer trench in the insulating isolation layer; forming an active region layer in the insulating isolation layer trench; forming a semiconductor device structure in and above the active region layer; characterized in that the carrier mobility of the active region layer is higher than that of the substrate. Said active region is formed of a material different from that of the substrate, the carrier mobility in the channel region is enhanced, thereby the device response speed is improved and the device performance is enhanced. Unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract translation: 本发明公开了一种制造半导体器件的方法，包括：在衬底上形成绝缘隔离层; 在绝缘隔离层中形成绝缘隔离层沟槽; 在绝缘隔离层沟槽中形成有源区; 在有源区域层中形成半导体器件结构; 其特征在于，有源区层的载流子迁移率高于基板的载流子迁移率。 所述有源区由不同于衬底的材料形成，通道区域中的载流子迁移率增强，从而提高了器件响应速度并提高了器件性能。 与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20120270165A1

公开(公告)日：2012-10-25

申请号：US13379242

申请日：2011-08-09

Applicant: Chunlong Li

Inventor： Chunlong Li

IPC: F27D9/00

CPC classification number: H01L21/28211 ,  H01L21/324

Abstract: The present invention discloses a heating method for maintaining a stable thermal budget. By following the primary procedure with a virtual procedure in such a manner that the total duration of the whole heating process remains constant, it is beneficial to maintain a stable thermal budget and further to maintain a stable device performance.

Abstract translation: 本发明公开了一种用于保持稳定的热预算的加热方法。 通过遵循具有虚拟过程的主要过程，使得整个加热过程的总持续时间保持恒定，维持稳定的热预算以及进一步维持稳定的设备性能是有益的。