公开(公告)号：US08179293B2

公开(公告)日：2012-05-15

申请号：US12954024

申请日：2010-11-24

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H03M1/12

CPC分类号： H03M1/1014

摘要： In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.

摘要翻译： 在一个实施例中，装置和方法降低了模数转换器（ADC）中的校准建立时间。 ADC具有参考电压供应。 参考电压源有一个输出。 滤波电容器耦合到参考电压电源输出。 隔离晶体管串联耦合在滤波电容和地之间。 隔离晶体管在ADC校准期间隔离滤波电容。

公开(公告)号：US07751516B2

公开(公告)日：2010-07-06

申请号：US11358148

申请日：2006-02-21

申请人： Andrew J. Castellano ,  Pieter Vorenkamp ,  Chun-Ying Chen

发明人： Andrew J. Castellano ,  Pieter Vorenkamp ,  Chun-Ying Chen

IPC分类号： H04L7/00

CPC分类号： H04L7/0008 ,  H04L7/0037

摘要： Inter-device adaptable interfacing clock skewing. The invention is operable in either one of both of a transmit mode and a receive mode to perform skewing of a transmitted and/or a received signal. The operational parameters including frequency and phase may be determined during auto detect/auto negotiation, they may be programmed externally, or they may be user selected in various embodiments. A device may include a clock generator, one or more divider, and one or more delay cells internally to the device. If desired, a high frequency clock is generated within the device and then divided down to generate the appropriate clock signal that supports the communication and interaction between multiple devices. Registers and/or pins may be used to select the clock frequency and phase of output clock signals. The present invention supports multiple Ethernet protocols between multiple devices including 10BaseT, 100BaseT, and 1000BaseT.

摘要翻译： 设备间适配性接口时钟偏移。 本发明可以在发射模式和接收模式两者中的任一个中操作，以执行发送和/或接收信号的偏移。 可以在自动检测/自动协商期间确定包括频率和相位的操作参数，它们可以在外部编程，或者可以在各种实施例中用户选择。 设备可以在设备内部包括时钟发生器，一个或多个分频器以及一个或多个延迟单元。 如果需要，在器件内产生高频时钟，然后分频，以产生支持多个器件之间通信和交互的适当时钟信号。 寄存器和/或引脚可用于选择时钟频率和输出时钟信号的相位。 本发明支持多个设备之间的多个以太网协议，包括10BaseT，100BaseT和1000BaseT。

公开(公告)号：US07705463B2

公开(公告)日：2010-04-27

申请号：US11473043

申请日：2006-06-23

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H01L23/52

CPC分类号： H01L29/92 ,  H01L29/94

摘要： The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance.

摘要翻译： 本发明涉及用于减小集成电路中的寄生电容的装置和方法。 该装置包括基板和偏置装置。 衬底具有设置在其上的电路，其中在衬底和电路的元件之间存在第一电容。 偏置器件DC将衬底的第一部分偏置到不同于衬底的第二部分的电压的电压，从而在衬底的第一部分和衬底的第二部分之间引起第二电容。 第二电容与第一电容串联。

公开(公告)号：US20090058699A1

公开(公告)日：2009-03-05

申请号：US12289460

申请日：2008-10-28

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H03M1/10

CPC分类号： H03M1/1014

摘要： In an embodiment, an apparatus and method reduces a calibration settling time in an analog-to-digital converter (ADC). The ADC has a reference voltage supply. The reference voltage supply has an output. A filter capacitor is coupled to the reference voltage supply output. An isolation transistor is series-coupled between the filter capacitor and ground. The isolation transistor isolates the filter capacitor during calibration of the ADC.

摘要翻译： 在一个实施例中，装置和方法降低了模数转换器（ADC）中的校准建立时间。 ADC具有参考电压供应。 参考电压源有一个输出。 滤波电容器耦合到参考电压电源输出。 隔离晶体管串联耦合在滤波电容和地之间。 隔离晶体管在ADC校准期间隔离滤波电容。

公开(公告)号：US20070120591A1

公开(公告)日：2007-05-31

申请号：US11585841

申请日：2006-10-25

申请人： Yee Cheung ,  Chun-Ying Chen

发明人： Yee Cheung ,  Chun-Ying Chen

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  H02M2001/0041

摘要： A charge pump includes a resistor divider connected between an output voltage node and ground and a comparator inputting a reference voltage at one input, and a divided voltage from the resistor divider at another input. A digital control circuit is enabled by the comparator. A first transistor and a second transistor are in series between an input voltage node and the ground, both transistors controlled by the digital control circuit. A pump capacitor is connected between to the output voltage node and between the first and second transistor, and being charged by turning the first and second transistors on and off. A first diode is between the pump capacitor and the input voltage node. A second diode between the pump capacitor and the output voltage node. A reservoir capacitor between the output voltage node and ground. The digital control circuit comprises a first shift register. The first transistor comprises a first plurality of parallel transistors, the first shift register includes any of a first plurality of DQ, RS or JK flip flops connected in series, and outputs of the flip flops control gates of the first plurality of parallel transistors.

摘要翻译： 电荷泵包括连接在输出电压节点和地之间的电阻分压器和在一个输入端输入参考电压的比较器，以及在另一个输入端分别来自电阻分压器的分压电压。 数字控制电路由比较器使能。 第一晶体管和第二晶体管串联在输入电压节点和地之间，两个晶体管都由数字控制电路控制。 泵浦电容器连接到输出电压节点之间，并且连接在第一和第二晶体管之间，并通过使第一和第二晶体管导通和关断而被充电。 第一个二极管位于泵电容器和输入电压节点之间。 泵电容器和输出电压节点之间的第二个二极管。 输出电压节点与地之间的储层电容。 数字控制电路包括第一移位寄存器。 第一晶体管包括第一多个并联晶体管，第一移位寄存器包括串联连接的第一多个DQ，RS或JK触发器中的任一个以及第一多个并联晶体管的触发器控制栅极的输出。

公开(公告)号：US07224156B2

公开(公告)日：2007-05-29

申请号：US11037186

申请日：2005-01-19

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： G05F3/16

CPC分类号： G05F1/56 ,  G05F1/575

摘要： A voltage regulator includes a first stage capable having a first current flowing through it. A second stage has a second current. A third stage is capable of outputting an output voltage and has a third current flowing through it. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.

摘要翻译： 电压调节器包括能够流过第一电流的第一级。 第二阶段有第二个电流。 第三级能够输出输出电压并且具有流经它的第三电流。 在基本为零的输出电流和最大输出电流之间，电压调节器的整个操作范围中，第一，第二和第三电流彼此成比例。 第一级驱动第二级作为低输入阻抗负载。

公开(公告)号：US20070117507A1

公开(公告)日：2007-05-24

申请号：US11580228

申请日：2006-10-13

申请人： Myles Wakayama ,  Dana Laub ,  Frank Carr ,  Afshin Mellati ,  David Ho ,  Hsiang-Bin Lee ,  Chun-Ying Chen ,  James Chang ,  Lawrence Burns ,  Young Shin ,  Patrick Pai ,  Iconomos Koullias ,  Ron Lipka ,  Luke Steigerwald ,  Alexandre Kral

发明人： Myles Wakayama ,  Dana Laub ,  Frank Carr ,  Afshin Mellati ,  David Ho ,  Hsiang-Bin Lee ,  Chun-Ying Chen ,  James Chang ,  Lawrence Burns ,  Young Shin ,  Patrick Pai ,  Iconomos Koullias ,  Ron Lipka ,  Luke Steigerwald ,  Alexandre Kral

IPC分类号： H04H1/00 ,  H04B1/28

CPC分类号： H03H11/04 ,  H03D3/008 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03D2200/0047 ,  H04B1/30

摘要： A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

摘要翻译： 直接转换卫星调谐器完全集成在公共基板上。 集成调谐器接收具有多个信道的RF信号，并将所选择的信道直接下变频到基带用于进一步处理。 集成调谐器包括片上本地振荡器产生，可调谐基带滤波器和DC偏移消除。 集成调谐器可以以完全差分的I / Q配置来实现，以改善电气性能。 整个直接转换卫星调谐器可以使用标准CMOS处理在单个半导体衬底上制造，具有最小的片外部件。 这里描述的调谐器配置不限于处理TV信号，并且可以用于将其它RF信号下变频到IF频率或基带。

公开(公告)号：US07139547B2

公开(公告)日：2006-11-21

申请号：US09995695

申请日：2001-11-29

申请人： Myles Wakayama ,  Dana Vincent Laub ,  Frank Carr ,  Afshin Mellati ,  David S. P. Ho ,  Hsiang-Bin Lee ,  Chun-Ying Chen ,  James Y. C. Chang ,  Lawrence M. Burns ,  Young Joon Shin ,  Patrick Pai ,  Iconomos A. Koullias ,  Ron Lipka ,  Luke Thomas Steigerwald ,  Alexandre Kral

发明人： Myles Wakayama ,  Dana Vincent Laub ,  Frank Carr ,  Afshin Mellati ,  David S. P. Ho ,  Hsiang-Bin Lee ,  Chun-Ying Chen ,  James Y. C. Chang ,  Lawrence M. Burns ,  Young Joon Shin ,  Patrick Pai ,  Iconomos A. Koullias ,  Ron Lipka ,  Luke Thomas Steigerwald ,  Alexandre Kral

IPC分类号： H04B1/28

CPC分类号： H03H11/04 ,  H03D3/008 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/165 ,  H03D2200/0025 ,  H03D2200/0043 ,  H03D2200/0047 ,  H04B1/30

摘要： A direct conversion satellite tuner is fully integrated on a common substrate. The integrated tuner receives an RF signal having a plurality of channels and down-converts a selected channel directly to baseband for further processing. The integrated tuner includes on-chip local oscillator generation, tunable baseband filters, and DC Offset cancellation. The integrated tuner can be implemented in a completely differential I/Q configuration for improved electrical performance. The entire direct conversion satellite tuner can be fabricated on a single semiconductor substrate using standard CMOS processing, with minimal off-chip components. The tuner configuration described herein is not limited to processing TV signals, and can be utilized to down-convert other RF signals to an IF frequency or baseband.

公开(公告)号：US20060237820A1

公开(公告)日：2006-10-26

申请号：US11473043

申请日：2006-06-23

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H01L29/00

CPC分类号： H01L29/92 ,  H01L29/94

摘要： The present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit. The apparatus includes a substrate and a biasing device. The substrate has a circuit disposed thereon, wherein a first capacitance exists between the substrate and an element of the circuit. The biasing device DC biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate, thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate. The second capacitance is in series with the first capacitance.

摘要翻译： 本发明涉及用于减小集成电路中的寄生电容的装置和方法。 该装置包括基板和偏置装置。 衬底具有设置在其上的电路，其中在衬底和电路的元件之间存在第一电容。 偏置器件DC将衬底的第一部分偏压到与衬底的第二部分的电压不同的电压，从而在衬底的第一部分和衬底的第二部分之间引起第二电容。 第二电容与第一电容串联。

公开(公告)号：US20060087780A1

公开(公告)日：2006-04-27

申请号：US11155739

申请日：2005-06-20

申请人： Chun-Ying Chen

发明人： Chun-Ying Chen

IPC分类号： H02H9/00

CPC分类号： G05F1/571

摘要： During start-up of a circuit having a high voltage supply and a low voltage supply, a backup bias generator (BBG) is used to avoid burnout and exceeding a breakdown voltage. The high voltage supply is powered on before the low voltage supply. The BBG generates bias in response to the high voltage supply being powered on. Once the low voltage supply is powered on and is stable, the BBG is shut down so that it does not interfere with normal operation of the circuit. The circuit can be separated into high and low supply domains without breakdown issues during power start-up, allowing for power and area optimization.

摘要翻译： 在启动具有高电压电源和低电压电源的电路时，使用备用偏置发生器（BBG）来避免烧坏并超过击穿电压。 高压电源在低电压供电之前通电。 BBG响应高电压供电而产生偏置。 一旦低压电源通电并且稳定，则BBG被关闭，使其不干扰电路的正常工作。 该电路可以分为高电源和低电源域，而在启动启动期间不会出现故障，从而实现功率和面积优化。