公开(公告)号：US20180373635A1

公开(公告)日：2018-12-27

申请号：US15631085

申请日：2017-06-23

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  David Asher ,  Wilson P. Snyder, II

IPC: G06F12/0846 ,  G06F12/0864 ,  G06F12/084

Abstract: Partition information includes entries that each include an entity identifier and associated cache configuration information. A controller manages memory requests originating from processor cores, including: comparing at least a portion of an address included in a memory request with tags stored in a cache to determine whether the memory request results in a hit or a miss, and comparing an entity identifier included in the memory request with stored entity identifiers to determine a matched entry. The cache configuration information associated with the entity identifier in a matched entry is updated based at least in part on a hit or miss result. The associated cache configuration information includes cache usage information that tracks usage of the cache by an entity associated with the particular entity identifier, and partition descriptors that each define a different group of one or more of the regions.

公开(公告)号：US09058463B1

公开(公告)日：2015-06-16

申请号：US14151748

申请日：2014-01-09

Applicant: Cavium, Inc.

Inventor： Shahid Ikram ,  Isam Akkawi ,  John Perveiler ,  David Asher ,  James Ellis

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/5045

Abstract: A new approach is proposed that contemplates systems and methods to support a hybrid verification framework (HVF) to design, verify, and implement design protocols for an integrated circuit (IC) chip such as a system-on-chip (SOC) and/or an application-specific integrated circuit (ASIC) chip. The framework creates a plurality of specifications in form of extended state transition tables for different phases of a design flow of the IC chip. The framework integrates and uses the extended state table-based specifications and the templates in all phases in the design flow, resulting in a tight revision loop of debug, verification, and validation across the phases of the design flow.

Abstract translation: 提出了一种新的方法，其考虑支持混合验证框架（HVF）以设计，验证和实施集成电路（IC）芯片（例如片上系统（SOC））和/或其中的集成电路（IC）芯片的设计协议的系统和方法 专用集成电路（ASIC）芯片。 该框架以IC芯片的设计流程的不同阶段的扩展状态转换表的形式形成多个规范。 该框架在设计流程的所有阶段集成并使用扩展状态表格规范和模板，从而在设计流程的各个阶段对调试，验证和验证进行了严格的修订循环。

公开(公告)号：US20180293114A1

公开(公告)日：2018-10-11

申请号：US15697736

申请日：2017-09-07

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  Isam Wadih Akkawi ,  David Asher ,  Michael Bertone ,  David Albert Carlson ,  Bradley Dobbie ,  Richard Eugene Kessler

IPC: G06F9/52

CPC classification number: G06F9/526 ,  G06F9/524

Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.

公开(公告)号：US20170220477A1

公开(公告)日：2017-08-03

申请号：US15013139

申请日：2016-02-02

Applicant: Cavium, Inc.

Inventor： Xiaodong Wang ,  Srilatha Manne ,  Bryan Wai Chin ,  Isam Akkawi ,  David Asher

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1045 ,  G06F11/3065 ,  G06F12/0811 ,  G06F12/126 ,  G06F2201/885 ,  G06F2212/1021 ,  G06F2212/1048 ,  G06F2212/502

Abstract: System and method determining metric for selective caching, comprising determining a result of an access to a cache for at least one tracked attribute; determining a count value for the at least one tracked attribute in a translation look-aside buffer entry corresponding to the access to the cache in accordance with the determined result; comparing the count value for the at least one tracked attribute with a threshold associated with the at least one tracked attribute; assigning the metric of sticky property to a cache line corresponding to the translation look-aside buffer entry when the count value for at least one of the at least one tracked attribute exceeds the threshold. Selective caching then assigns different protection status to the cache lines with and without sticky property; and evicting a cache line in accordance with a cache eviction policy starting with the cache lines with the lowest protection status.

公开(公告)号：US09355206B2

公开(公告)日：2016-05-31

申请号：US14288121

申请日：2014-05-27

Applicant: Cavium, Inc.

Inventor： Shahid Ikram ,  Isam Akkawi ,  John Perveiler ,  David Asher ,  James Ellis

IPC: G06F17/50 ,  G06F11/273 ,  G06F15/78 ,  G06F11/267

CPC classification number: G06F17/5081 ,  G06F11/267 ,  G06F11/2733 ,  G06F15/78 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/5045

Abstract: A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.

Abstract translation: 提出了一种新方法，其考虑了用于支持IC设计协议的自动功能覆盖生成和管理的系统和方法。 所提出的方法利用IC设计协议的基于表的高级（例如，事务级）规范，其中状态表是可读的并且易于管理（例如，以ASCII格式），以便自动生成功能覆盖 该IC设计协议包括但不限于覆盖点，协议转换和/或事务覆盖。 然后，通过形式验证，自动生成的功能覆盖，并在覆盖生成和管理过程中在寄存器传输级（RTL）下进行模拟。 然后分析形式验证和模拟运行的覆盖数据，并用于指导和修改基于覆盖的闭环IC设计流程中的IC设计协议。

公开(公告)号：US20180293070A1

公开(公告)日：2018-10-11

申请号：US15609225

申请日：2017-05-31

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  Isam Wadih Akkawi ,  David Asher ,  Michael Bertone ,  David Albert Carlson ,  Bradley Dobbie ,  Richard Eugene Kessler

IPC: G06F9/30 ,  G06F9/52

Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.

公开(公告)号：US10002218B2

公开(公告)日：2018-06-19

申请号：US15065799

申请日：2016-03-09

Applicant: CAVIUM, INC.

Inventor： Shahid Ikram ,  Isam Akkawi ,  Richard Eugene Kessler ,  James Ellis ,  David Asher

IPC: G06F17/50 ,  G06F12/0817

CPC classification number: G06F17/5045 ,  G06F12/0817 ,  G06F2212/622

Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.

公开(公告)号：US20160267209A1

公开(公告)日：2016-09-15

申请号：US15065799

申请日：2016-03-09

Applicant: CAVIUM, INC.

Inventor： Shahid Ikram ,  Isam Akkawi ,  Richard Eugene Kessler ,  James Ellis ,  David Asher

IPC: G06F17/50 ,  G06F12/08

CPC classification number: G06F17/5045 ,  G06F12/0817 ,  G06F2212/622

Abstract: A system includes a formal verification engine running on a host and a protocol checking engine. The formal verification engine automatically generates and formally verifies a reference specification that includes a plurality of extended state tables for an integrated circuit (IC) design protocol of a chip at architectural level. The formal verification engine is further configured to automatically generate a plurality of self-contained services from the plurality of extended state tables. A self-contained service of the plurality of self-contained services is randomly and atomically executable. The self-contained service of the plurality of self-contained services changes responsive to the IC design protocol changing. The protocol checking engine checks and validates completeness and correctness of the self-contained service of the reference specification.

Abstract translation: 系统包括在主机上运行的形式验证引擎和协议检查引擎。 形式验证引擎自动生成并正式验证包括用于架构级芯片的集成电路（IC）设计协议的多个扩展状态表的参考规范。 形式验证引擎还被配置为从多个扩展状态表自动生成多个独立服务。 多个自包含服务的独立服务是随机和原子可执行的。 响应于IC设计协议改变，多个独立服务的独立服务改变。 协议检查引擎检查并验证参考规范的自包含服务的完整性和正确性。

公开(公告)号：US20160140060A1

公开(公告)日：2016-05-19

申请号：US14541902

申请日：2014-11-14

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  David Asher ,  Brad Dobbie ,  Tom Hummel ,  Daniel Dever

IPC: G06F13/16 ,  G06F12/10 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/404 ,  G06F13/4068 ,  G06F2212/65 ,  G06F2212/68

Abstract: A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.

Abstract translation: 主板包括多个插座，每个插座配置为接受集成电路。 第一插座中的第一集成电路包括一个或多个核心和至少一个缓冲器。 第二插座中的第二集成电路包括一个或多个核和至少一个缓冲器。 通信电路将消息传送到耦合到不同插座的集成电路的缓冲器。 第一集成电路上的第一核心被配置为通过通信电路将对应于多种类型的指令的消息发送到第二集成电路上的第二核心。 第二集成电路的缓冲器足够大以同时存储允许在第一集成电路上的核心从第二类型获得的最大数量的指令，并且仍然具有用于一个或多个指令的足够的存储空间 的第一种类型。

公开(公告)号：US20180293113A1

公开(公告)日：2018-10-11

申请号：US15609211

申请日：2017-05-31

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  Isam Wadih Akkawi ,  David Asher ,  Michael Bertone ,  David Albert Carlson ,  Bradley Dobbie ,  Richard Eugene Kessler

IPC: G06F9/52 ,  G06F9/30

CPC classification number: G06F9/526 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/3009 ,  G06F9/4881 ,  G06F9/528 ,  G06F9/546

Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.