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公开(公告)号：US20180293114A1
公开(公告)日：2018-10-11
申请号：US15697736
申请日：2017-09-07
Applicant: Cavium, Inc.
Inventor： Shubhendu Sekhar Mukherjee , Isam Wadih Akkawi , David Asher , Michael Bertone , David Albert Carlson , Bradley Dobbie , Richard Eugene Kessler
IPC: G06F9/52
Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock stored in a particular memory location, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts using associated operation messages for accessing the particular memory location, or (2) an unlock operation corresponding to a particular lock stored in a particular memory location, releasing the particular lock from the first thread using an associated operation message for accessing the particular memory location. Selected operation messages associated with an unlock operation are prioritized over operation messages associated with a lock operation.
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公开(公告)号：US20180293113A1
公开(公告)日：2018-10-11
申请号：US15609211
申请日：2017-05-31
Applicant: Cavium, Inc.
Inventor： Shubhendu Sekhar Mukherjee , Isam Wadih Akkawi , David Asher , Michael Bertone , David Albert Carlson , Bradley Dobbie , Richard Eugene Kessler
CPC classification number: G06F9/526 , G06F9/30072 , G06F9/30079 , G06F9/3009 , G06F9/4881 , G06F9/528 , G06F9/546
Abstract: Managing instructions on a processor includes: executing threads having access to a stored library of operations. For a first thread executing on the first processor core, for each instruction included in the first thread and identified as being associated with a lock operation corresponding to a particular lock, the managing includes determining if the particular lock has already been acquired for another thread executing on a processor core other than the first processor core, and if so, continuing to perform the lock operation for multiple attempts using a hardware lock operation different from the lock operation in the stored library, and if not, acquiring the particular lock for the first thread. The hardware lock operation performs a modified atomic operation that changes a result of the hardware lock operation for failed attempts to acquire the particular lock relative to a result of the lock operation in the stored library.
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公开(公告)号：US20180293070A1
公开(公告)日：2018-10-11
申请号：US15609225
申请日：2017-05-31
Applicant: Cavium, Inc.
Inventor： Shubhendu Sekhar Mukherjee , Isam Wadih Akkawi , David Asher , Michael Bertone , David Albert Carlson , Bradley Dobbie , Richard Eugene Kessler
Abstract: Managing instructions on a processor includes: identifying selected instructions as being associated with operations from a stored library of operations. The identifying includes, for instructions included in a particular thread executing on the processor, identifying first/second subsets of the instructions as being associated with a lock/unlock operation based on predetermined characteristics of the instructions. Managing lock/unlock operations associated with the selected instructions that are issued on a first processor core includes, for each instruction included in a first thread and identified as being associated with a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to attempt to acquire the particular lock for multiple attempts using a lock operation different from the lock operation in the stored library.
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公开(公告)号：US20180293100A1
公开(公告)日：2018-10-11
申请号：US15609217
申请日：2017-05-31
Applicant: Cavium, Inc.
Inventor： Shubhendu Sekhar Mukherjee , Isam Wadih Akkawi , David Asher , Michael Bertone , David Albert Carlson , Bradley Dobbie , Richard Eugene Kessler
CPC classification number: G06F9/3009 , G06F9/3004 , G06F9/30072 , G06F9/30079 , G06F9/3834 , G06F9/4881 , G06F9/526 , G06F9/546
Abstract: Managing lock and unlock operations for a first thread executing on a first processor core includes, for each instruction included in the first thread and identified as being associated with: (1) a lock operation corresponding to a particular lock, in response to determining that the particular lock has already been acquired, continuing to perform the lock operation for multiple attempts during which the first processor core is not able to execute threads other than the first thread, or (2) an unlock operation corresponding to a particular lock, releasing the particular lock from the first thread. Prioritization of selected messages sent over interconnection circuitry configured to connect each processor core to a memory system of the processor is preserved. The selected messages associated with instructions identified as being associated with an unlock operation are prioritized over messages associated with instructions identified as being associated with a lock operation.
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