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    Method and apparatus for a direct current (DC) coupled input buffer
    2.
    发明授权
    Method and apparatus for a direct current (DC) coupled input buffer 有权
    用于直流（DC）耦合输入缓冲器的方法和装置

    公开(公告)号：US07436216B1

    公开(公告)日：2008-10-14

    申请号：US11452858

    申请日：2006-06-14

    申请人： Brian T. Brunn ,  Michael A. Nix ,  Ahmed Younis

    发明人： Brian T. Brunn ,  Michael A. Nix ,  Ahmed Younis

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F3/4521 ,  H03F3/45632 ,  H03F2203/45101 ,  H03F2203/45354 ,  H03F2203/45588 ,  H03F2203/45592 ,  H03F2203/45616 ,  H03F2203/45681

    摘要： A method and apparatus for combining an alternating current (AC) coupling technique with a low frequency restoration technique to provide AC coupling with low frequency restoration of the attenuated low frequency content. The low frequency restoration circuit operates to extract low frequency information prior to being high-pass filtered by the AC coupling circuit. The low frequency restoration circuit then buffers the low frequency information through a low frequency restoration amplifier, applies a programmable common mode voltage to the buffered, low frequency information, and then restores the buffered, common mode adjusted, low frequency information to the output of the AC coupling circuit.

    摘要翻译： 一种用于将交流（AC）耦合技术与低频恢复技术组合以提供与所述衰减低频内容的低频恢复的AC耦合的方法和装置。 在由AC耦合电路进行高通滤波之前，低频恢复电路用于提取低频信息。 然后，低频恢复电路通过低频恢复放大器缓冲低频信息，将可编程共模电压施加到缓冲的低频信息，然后将缓冲的共模调制的低频信息恢复到 交流耦合电路。

    Ring oscillators with improved signal-path matching for high-speed data communications
    3.
    发明授权
    Ring oscillators with improved signal-path matching for high-speed data communications 有权
    环形振荡器具有改进的信号路径匹配，用于高速数据通信

    公开(公告)号：US06501339B1

    公开(公告)日：2002-12-31

    申请号：US09927146

    申请日：2001-08-10

    申请人： Ahmed Younis ,  Moises E. Robinson ,  Michael A. Nix ,  Brian T. Brunn

    发明人： Ahmed Younis ,  Moises E. Robinson ,  Michael A. Nix ,  Brian T. Brunn

    IPC分类号： H03B524

    CPC分类号： H03L7/0995 ,  H03K3/0315 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

    摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.

    摘要翻译： 电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。 许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。 常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。 因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。 一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。 另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。 并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。 这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。

    Multiplying phase detector for use in a random data locked loop architecture
    4.
    发明授权
    Multiplying phase detector for use in a random data locked loop architecture 有权
    乘法相位检测器用于随机数据锁定环路架构

    公开(公告)号：US07142622B1

    公开(公告)日：2006-11-28

    申请号：US10421248

    申请日：2003-04-22

    申请人： Brian T. Brunn ,  Ahmed Younis

    发明人： Brian T. Brunn ,  Ahmed Younis

    IPC分类号： H03D3/24

    CPC分类号： H03D13/004

    摘要： A multiplying phase detector includes a 1st multiplier, a 2nd multiplier and a phase error generation module. The 1st multiplier is operably coupled to multiple an incoming data stream, which is a random data pattern, with a 1st clock, which is in-phase with the incoming stream of data and is one-half the rate of the incoming stream of data, to produce a 1st product. In this instance, the 1st product represents missing transitions in the incoming stream of data. The 2nd multiplier is operably coupled to multiply the 1st product with the incoming data stream to produce a modified stream of data. The phase error generation module is operably coupled to generate a phase error based on the modified stream of data and a 2nd clock, where the phase error represents a phase offset between the modified stream of data and the 2nd clock.

    摘要翻译： 乘法相位检测器包括1乘法器，2乘法器和相位误差产生模块。 1＆lt; ST＆gt;乘法器可操作地耦合到具有1秒时钟的多个输入数据流，其是随机数据模式，其与进入流同步 的数据，并且是传入数据流的一半速率，以产生1 ST 产品。 在这种情况下，1＆lt; ST＆gt;产品表示输入的数据流中的丢失的转换。 2乘法器乘法器可操作地耦合以将第一产品与输入数据流相乘以产生经修改的数据流。 相位误差产生模块可操作地耦合以产生基于经修改的数据流和第二时钟的相位误差，其中相位误差表示修改的数据流与第二时钟之间的相位偏移 nd 时钟。

    High-speed wide bandwidth data detection circuit
    5.
    发明授权
    High-speed wide bandwidth data detection circuit 有权
    高速宽带数据检测电路

    公开(公告)号：US07224760B1

    公开(公告)日：2007-05-29

    申请号：US10421512

    申请日：2003-04-22

    申请人： Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

    发明人： Shahriar Rokhsaz ,  Moises E. Robinson ,  Ahmed Younis ,  Brian T. Brunn

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

    摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.

    摘要翻译： 高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。 相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。 相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。 数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。 环路滤波器可操作地耦合以将受控电流转换成受控电压。 压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。

    Clock and data recovery phase-locked loop
    6.
    发明授权
    Clock and data recovery phase-locked loop 有权
    时钟和数据恢复锁相环

    公开(公告)号：US06977959B2

    公开(公告)日：2005-12-20

    申请号：US10346435

    申请日：2003-01-17

    申请人： Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

    发明人： Brian T. Brunn ,  Ahmed Younis ,  Shahriar Rokhsaz

    IPC分类号： H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10 ,  H04L7/033 ,  H04B1/38 ,  H03D3/24

    CPC分类号： H04L7/0331 ,  H03D13/003 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/10

    摘要： A clock recovery circuit that operates at a clock speed equal to one-half the input data rate is presented. The clock recovery circuit uses dual input latches to sample the incoming serial data on both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other.

    摘要翻译： 提出了以等于输入数据速率的一半的时钟速度工作的时钟恢复电路。 时钟恢复电路使用双输入锁存器在半速率时钟信号的上升沿和下降沿对采样的串行数据进行采样，以提供等效的全数据速率时钟恢复。 时钟恢复电路用于保持输入串行数据位中心的半速率时钟转换。 时钟恢复电路包括相位检测器，电荷泵，受控振荡模块和反馈模块。 相位检测器产生关于输入数据信号中的相位和数据转换到电荷泵的信息。 通常，电路是延迟不敏感的，并且相对于彼此交错地接收相位和转换信息。

    Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors
    7.
    发明授权
    Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors 有权

    公开(公告)号：US06784822B1

    公开(公告)日：2004-08-31

    申请号：US10693215

    申请日：2003-10-24

    申请人： Michael A. Nix ,  Ahmed Younis

    发明人： Michael A. Nix ,  Ahmed Younis

    IPC分类号： H03M138

    CPC分类号： H03M1/16 ,  H03M1/60

    摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

    Method and circuit for determining frequency and time variations between electronic signals
    8.
    发明授权
    Method and circuit for determining frequency and time variations between electronic signals 有权
    用于确定电子信号之间频率和时间变化的方法和电路

    公开(公告)号：US06621307B1

    公开(公告)日：2003-09-16

    申请号：US10224978

    申请日：2002-08-20

    申请人： Ahmed Younis ,  Michael A. Nix

    发明人： Ahmed Younis ,  Michael A. Nix

    IPC分类号： H03D1300

    CPC分类号： H03D13/006

    摘要： A method and circuit for determining variation between an input clock signal (CLK0) and a reference clock signal (REFCLK) is provided. A plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be generated from a single input clock signal (CLK0). The plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be sampled at successive periodic intervals occurring relative to the reference clock signal (REFCLK). For each of the time shifted input clock signals (CLK0, CLK1, . . . , CLK09), a sampled value for a succeeding and a preceding periodic interval can be compared to determine whether there is a variation between an input clock signal (CLK0) and a reference clock signal (REFCLK).

    摘要翻译： 提供了一种用于确定输入时钟信号（CLK0）和参考时钟信号（REFCLK）之间的变化的方法和电路。 可以从单个输入时钟信号（CLK0）产生多个时移输入时钟信号（CLK0，CLK1，...，CLK09）。 可以以相对于参考时钟信号（REFCLK）发生的连续周期性间隔对多个时移输入时钟信号（CLK0，CLK1，...，CLK09）进行采样。 对于每个时移输入时钟信号（CLK0，CLK1，...，CLK09），可以对后续周期和前一周期间隔的采样值进行比较，以确定输入时钟信号（CLK0） 和参考时钟信号（REFCLK）。

    Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors
    9.
    发明授权
    Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors 有权
    使用频率检测器和时间检测器的折叠模数转换器（ADC）的方法和电路

    公开(公告)号：US06677879B1

    公开(公告)日：2004-01-13

    申请号：US10224976

    申请日：2002-08-20

    申请人： Michael A. Nix ,  Ahmed Younis

    发明人： Michael A. Nix ,  Ahmed Younis

    IPC分类号： H03M112

    CPC分类号： H03M1/16 ,  H03M1/60

    摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.

    摘要翻译： 输入模拟信号（105或405）的电压可以转换为频率取决于模拟输入信号（135或435）的信号。 分频器（115或415）可以被配置为将频率相关信号转换成分频信号（140或440）。 第一频率检测器（420a）或时间检测器（120a）可被配置为确定分频信号的频率，从而产生第一输出信号（145a或445a）。 第二频率检测器（420b）或时间检测器（120b）可以被配置为确定频率相关或非频率分频信号的频率，从而产生第二输出信号（145b或445b）。 第一和第二输出信号可以被后处理以产生代表输入模拟信号的数字输出信号（130或430）。

    High-speed synchronous counters with reduced logic complexity
    10.
    发明授权
    High-speed synchronous counters with reduced logic complexity 有权

    公开(公告)号：US07092480B1

    公开(公告)日：2006-08-15

    申请号：US10977304

    申请日：2004-10-29

    申请人： Ahmed Younis

    发明人： Ahmed Younis

    IPC分类号： H03K23/54 ,  H03H11/26

    CPC分类号： H03K23/54 ,  H03K23/548 ,  H03K23/588

    摘要： Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.