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公开(公告)号：US20090006765A1
公开(公告)日：2009-01-01
申请号：US11770107
申请日：2007-06-28
申请人： Ben-Zion Friedman , Ohad Falik
发明人： Ben-Zion Friedman , Ohad Falik
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901
摘要： Disclosed is a system and method for storing a plurality of data packets in a plurality of memory buffers in a cache memory for reducing cache conflicts. The method includes determining size of each of a plurality of data packets; storing a first data packet of the plurality of data packets starting from a first address in a first memory buffer of the plurality of memory buffers; determining an offset based on the size of the first data packet; and storing a second data packet in a second buffer starting from a second address based on the offset.
摘要翻译： 公开了一种用于将多个数据分组存储在高速缓冲存储器中的多个存储器缓冲器中用于减少高速缓存冲突的系统和方法。 该方法包括确定多个数据分组中的每一个的大小; 从所述多个存储器缓冲器的第一存储器缓冲器中的第一地址开始存储所述多个数据分组的第一数据分组; 基于所述第一数据分组的大小确定偏移量; 以及基于所述偏移从第二地址开始将第二数据分组存储在第二缓冲器中。
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公开(公告)号：US20140304488A1
公开(公告)日：2014-10-09
申请号：US14312669
申请日：2014-06-23
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
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公开(公告)号：US20080301398A1
公开(公告)日：2008-12-04
申请号：US11757103
申请日：2007-06-01
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
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公开(公告)号：US08799620B2
公开(公告)日：2014-08-05
申请号：US11757103
申请日：2007-06-01
CPC分类号： G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
摘要翻译： 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
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公开(公告)号：US20130262868A1
公开(公告)日：2013-10-03
申请号：US13839080
申请日：2013-03-15
申请人： Ben-Zion Friedman , Eliezer Tamir , Eliel Louzoun , Ohad Falik
发明人： Ben-Zion Friedman , Eliezer Tamir , Eliel Louzoun , Ohad Falik
IPC分类号： H04L9/06
CPC分类号： H04L9/0618 , G06F21/72 , H04L63/0485
摘要： Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.
摘要翻译： 公开了用于在网络设备的输入/输出设备和在网络设备上操作的第一处理元件之间交换密钥的示例。 具有与第一处理元件相关联的目的地的数据可以被输入/输出设备接收。 交换的密钥可以用于加密接收的数据。 然后，加密数据可以被发送到至少部分地保存在用于网络设备的存储器中的缓冲器。 存储器可以被布置为使得能够利用在网络设备上操作的至少第二处理元件来共享缓冲器。 还公开了用于处理元件接收在缓冲器中存储加密数据的指示的示例。 处理元件然后可以从缓冲器获得加密的数据，并使用所交换的密钥解密数据。
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公开(公告)号：US07793071B2
公开(公告)日：2010-09-07
申请号：US11770107
申请日：2007-06-28
申请人： Ben-Zion Friedman , Ohad Falik
发明人： Ben-Zion Friedman , Ohad Falik
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901
摘要： Disclosed is a system and method for storing a plurality of data packets in a plurality of memory buffers in a cache memory for reducing cache conflicts. The method includes determining size of each of a plurality of data packets; storing a first data packet of the plurality of data packets starting from a first address in a first memory buffer of the plurality of memory buffers; determining an offset based on the size of the first data packet; and storing a second data packet in a second buffer starting from a second address based on the offset.
摘要翻译： 公开了一种用于将多个数据分组存储在高速缓冲存储器中的多个存储器缓冲器中用于减少高速缓存冲突的系统和方法。 该方法包括确定多个数据分组中的每一个的大小; 从所述多个存储器缓冲器的第一存储器缓冲器中的第一地址开始存储所述多个数据分组的第一数据分组; 基于所述第一数据分组的大小确定偏移量; 以及基于所述偏移从第二地址开始将第二数据分组存储在第二缓冲器中。
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公开(公告)号：US08543796B2
公开(公告)日：2013-09-24
申请号：US12290962
申请日：2008-11-05
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
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公开(公告)号：US20130132636A1
公开(公告)日：2013-05-23
申请号：US13690931
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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公开(公告)号：US20130091317A1
公开(公告)日：2013-04-11
申请号：US13691016
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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公开(公告)号：US20110208925A1
公开(公告)日：2011-08-25
申请号：US12861439
申请日：2010-08-23
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译： 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
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