公开(公告)号：US09472615B2

公开(公告)日：2016-10-18

申请号：US14598119

申请日：2015-01-15

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/0634 ,  H01L29/063 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/6681 ,  H01L29/7823 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A fin-shaped field-effect transistor (finFET) device is provided. The finFET device includes a substrate material with a top surface and a bottom surface. The finFET device also includes a well region formed in the substrate material. The well region may include a first type of dopant. The finFET device also includes a fin structure disposed on the top surface of the substrate material. A portion of the fin structure may include the first type of dopant. The finFET device also includes an oxide material disposed on the top surface of the substrate material and adjacent to the portion of the fin structure. The finFET device also includes a first epitaxial material disposed over a portion of the fin structure. The first epitaxial material may include a second type of dopant.

Abstract translation: 提供了一种鳍状场效应晶体管（finFET）器件。 finFET器件包括具有顶表面和底表面的衬底材料。 finFET器件还包括形成在衬底材料中的阱区。 阱区可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上的翅片结构。 翅片结构的一部分可以包括第一类型的掺杂剂。 finFET器件还包括设置在衬底材料的顶表面上并且与鳍结构的部分相邻的氧化物材料。 finFET器件还包括设置在鳍结构的一部分上的第一外延材料。 第一外延材料可以包括第二类型的掺杂剂。

公开(公告)号：US09536880B2

公开(公告)日：2017-01-03

申请号：US14704511

申请日：2015-05-05

Applicant: Broadcom Corporation

Inventor： Qintao Zhang ,  Aimin Xing

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/78 ,  H01L29/167 ,  H01L21/265

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.

Abstract translation: 描述制造具有多个阈值电压的器件（例如，FDSOI器件）的方法。 一种方法包括提供靠近绝缘（例如，掩埋氧化物（BOX）层）的界面的第一固定电荷区域和用于第一器件的半导体衬底。 第一充电区域具有固定电荷的第一配置。 该方法还包括提供靠近绝缘层和用于第二器件的半导体衬底的界面的第二固定电荷区域。 第二充电区域具有与第一配置不同的固定电荷的第二配置。

公开(公告)号：US09379212B1

公开(公告)日：2016-06-28

申请号：US14611134

申请日：2015-01-30

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Shom Surendran Ponoth ,  Akira Ito

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L23/66

CPC classification number: H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/28114 ,  H01L23/66 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract translation: 具有增加的漏极 - 源极电压（Vds）的MOS器件包括沉积在衬底上的源极区域和漏极区域。 栅极区域包括延伸漏极区域的内部间隔物。 内部间隔件形成附接到隔离间隔件，隔离间隔件将漏极区域与栅极区域隔离。 内部间隔件被配置为延伸漏极区域以修改MOS器件的导电带的一部分中的电场。

公开(公告)号：US20160190281A1

公开(公告)日：2016-06-30

申请号：US14611134

申请日：2015-01-30

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Shom Surendran Ponoth ,  Akira Ito

IPC: H01L29/66 ,  H01L23/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/28114 ,  H01L23/66 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract translation: 具有增加的漏极 - 源极电压（Vds）的MOS器件包括沉积在衬底上的源极区域和漏极区域。 栅极区域包括延伸漏极区域的内部间隔物。 内部间隔件形成附接到隔离间隔件，隔离间隔件将漏极区域与栅极区域隔离。 内部间隔件被配置为延伸漏极区域以修改MOS器件的导电带的一部分中的电场。

公开(公告)号：US09634014B2

公开(公告)日：2017-04-25

申请号：US14692552

申请日：2015-04-21

Applicant: Broadcom Corporation

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L27/112 ,  H01L21/28 ,  H01L23/525 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3115

CPC classification number: H01L27/11206 ,  G11C17/146 ,  H01L21/26586 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/31155 ,  H01L23/5252 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/7851

Abstract: A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

公开(公告)号：US20160300838A1

公开(公告)日：2016-10-13

申请号：US14704511

申请日：2015-05-05

Applicant: Broadcom Corporation

Inventor： Qintao Zhang ,  Aimin Xing

IPC: H01L27/092 ,  H01L21/84 ,  H01L21/265 ,  H01L29/78 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.

Abstract translation: 描述制造具有多个阈值电压的器件（例如，FDSOI器件）的方法。 一种方法包括提供靠近绝缘（例如，掩埋氧化物（BOX）层）的界面的第一固定电荷区域和用于第一器件的半导体衬底。 第一充电区域具有固定电荷的第一配置。 该方法还包括提供靠近绝缘层和用于第二器件的半导体衬底的界面的第二固定电荷区域。 第二充电区域具有与第一配置不同的固定电荷的第二配置。

公开(公告)号：US20160276355A1

公开(公告)日：2016-09-22

申请号：US14692552

申请日：2015-04-21

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L27/112 ,  H01L21/28 ,  H01L21/265 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L23/525 ,  H01L21/3115

CPC classification number: H01L27/11206 ,  G11C17/146 ,  H01L21/26586 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/31155 ,  H01L23/5252 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/7851

Abstract: A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

Abstract translation: 可编程单元包括分离栅结构。 分离栅极结构包括薄栅极电介质区域和设置在栅极导体下方的厚栅极电介质区域。 厚氧化物区域的厚度大于薄氧化物区域的厚度。 可以使用角度掺杂来制造可编程单元以掺杂与薄介电区域相关联的区域。