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公开(公告)号：US10025143B2
公开(公告)日：2018-07-17
申请号：US15110230
申请日：2015-11-13
Inventor： Xiaofei Yang , Yuqing Yang , Yanxia Xin , Zailong Mo , Xue Jiang , Xun Mou
IPC: G02F1/1339 , G02F1/1343 , G02F1/1362 , G02F1/1333 , G02F1/1368
Abstract: An array substrate and a fabrication method thereof and a display device are provided. The array substrate comprises: a base substrate; a plurality of gate lines and a plurality of data lines formed on the base substrate, the plurality of gate lines and the plurality of data lines intersecting with each other to define a plurality of sub-pixels, each of the sub-pixels including a thin film transistor and a pixel electrode, and the plurality of sub-pixels including a first sub-pixel; a passivation layer formed on the base substrate and covering the gate lines, the data lines and the thin film transistor, a via hole being provided in the passivation layer and the pixel electrode being formed on the passivation layer and connected with a drain electrode or a source electrode of the thin film transistor through the via hole in each of the sub-pixels; and a first spacer, provided in the via hole of the first sub-pixel.
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公开(公告)号：US11719983B2
公开(公告)日：2023-08-08
申请号：US16986748
申请日：2020-08-06
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yang Yue , Qi Yao , Yong Yu , Hua Huang , Tong Yang , Shi Shu , Chuanxiang Xu , Xue Jiang , Haitao Huang , Xiang Li , Zhao Cui
IPC: G02F1/1347 , G02F1/1335 , G02F1/13357 , G02F1/1339 , G02F1/1343 , G02F1/1362
CPC classification number: G02F1/1347 , G02F1/13394 , G02F1/13396 , G02F1/13398 , G02F1/13471 , G02F1/133512 , G02F1/133514 , G02F1/133528 , G02F1/133617 , G02F1/134309 , G02F1/136286 , G02F1/133548 , G02F1/133614 , G02F2201/121 , G02F2201/123
Abstract: The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: a first medium and a first spacer wall between the first substrate and the second substrate, wherein the first sub-panel has filter pixels arranged at intervals, the first spacer wall is black and arranged along spaces between filter pixels, and a dielectric coefficient of the first spacer wall is greater than that of the first medium; and a second sub-panel on a light emergent side of the first sub-panel and including a second medium and a second spacer wall between the third substrate and the fourth substrate, wherein the second sub-panel has display pixels arranged at intervals, the second spacer wall is black and arranged along spaces between display pixels, and a dielectric coefficient of the second spacer wall is greater than that of the second medium.
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公开(公告)号：US11637166B2
公开(公告)日：2023-04-25
申请号：US16651551
申请日：2019-11-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yingwei Liu , Qi Yao , Ke Wang , Zhanfeng Cao , Zhiwei Liang , Muxin Di , Guangcai Yuan , Xue Jiang , Dongni Liu
Abstract: The present disclosure relates to a method of manufacturing an array substrate. The method of manufacturing an array substrate may include forming a main via hole in a substrate, filling a first conductive material in the main via hole, and forming a pixel circuit layer on a first surface of the substrate. The pixel circuit layer may include a first via hole. An orthographic projection of the first via hole on the substrate may at least partially overlap the corresponding main via hole.
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公开(公告)号：US20190088179A1
公开(公告)日：2019-03-21
申请号：US16056476
申请日：2018-08-06
Inventor： Dexiong Song , Zhiyong Yang , Shihua Huang , Wei He , Jing Wang , Liwei Huang , Xue Jiang , Wei Li , Chao Fu
IPC: G09G3/00 , G09G3/3258 , G09G3/20
Abstract: A test display panel is configured for application to a lighting test, and includes a plurality of reference voltage input terminals and a plurality of sub-pixels. The reference voltage input terminals are in a one-to-one correspondence to the sub-pixels. The display panel further includes a reference voltage supply circuit and a plurality of reference voltage lines. The sub-pixels include a plurality of first sub-pixels, second sub-pixels, and third sub-pixels having different colors. The reference voltage lines include a first reference voltage line, a second reference voltage line, and a third reference voltage line, each corresponding to respective sub-pixels. The reference voltage supply circuit is configured to provide reference voltages to the plurality of reference voltage lines in a time division manner. The reference voltage lines are electrically coupled to respective reference voltage input terminals of the sub-pixels.
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公开(公告)号：US20180108287A1
公开(公告)日：2018-04-19
申请号：US15555326
申请日：2017-01-18
Inventor： Xue Jiang , Xinghua Li , Seungyik Park
CPC classification number: G09G3/2074 , G09G3/2003 , G09G3/3614 , G09G3/3655 , G09G3/3685 , G09G2310/027 , G09G2310/061 , G09G2320/0204 , G09G2320/0247 , G09G2320/0257 , G09G2320/0271 , G09G2320/0666
Abstract: Exemplary embodiments of the present disclosure relate to a system and method for image processing, and a display device. The system comprises: a greyscale value selection module for selecting a plurality of color greyscale values for each sub-pixel, the sub-pixel being used for displaying an image; an optimal common voltage determination module for determining an optimal common voltage of each sub-pixel according to the selected color greyscale values for each sub-pixel; a uniformity determination module comprising a flicker uniformity determination module and a common voltage uniformity determination module, the flicker uniformity determination module being used for determining the flicker uniformity of each sub-pixel, the common voltage uniformity determination module being used for determining the common voltage uniformity of each sub-pixel according to the determined flicker uniformity of each sub-pixel; and an image compensation module for compensating each sub-pixel according to at least one of the optimal common voltage of each sub-pixel and the common voltage uniformity of each sub-pixel, thereby improving the residual image and flicker uniformity at the time of image display.
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Patent Agency Ranking
公开(公告)号：US11200819B2
公开(公告)日：2021-12-14
申请号：US16760366
申请日：2019-01-07
IPC: G09G3/00 , G06F1/18 , H01L27/32 , G09G3/3291
Abstract: A display substrate and a manufacturing method thereof, a display panel, a display motherboard and a testing method thereof, and a display device are provided in the present disclosure. The display substrate is provided with a display region and at least a wiring region outside the display region. The display substrate includes a base substrate and a plurality of connection structures on the base substrate. The plurality of connection structures are connected to a plurality of edge signal terminals through a control module. All of the plurality of connection structures, the plurality of edge signal terminals and the control module are located in the wiring region. The plurality of edge signal terminals are located on an edge of the wiring region. The control circuit is configured to control the connection or disconnection between the plurality of signal terminals and the plurality of connection structures.
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公开(公告)号：US11145247B2
公开(公告)日：2021-10-12
申请号：US16642361
申请日：2019-08-12
Inventor： Xue Jiang , Wei He , Zhiyong Yang , Jing Wang , Liwei Huang , Xiaohong Chen , Lihong Wu
IPC: G09G3/3225
Abstract: A display module Gamma correction method includes: obtaining corrected Gamma register values corresponding to binding points of a grayscale by correcting register values of s binding points selected from a set of m binding points of the grayscale based on a group of initial Gamma register values that correspond to the m binding points and a target Gamma curve; selecting, from x sets of alternate Gamma register values wherein each set corresponds to m binding points and the initial Gamma register values, a set of Gamma register values used for Gamma correction of the display module(s) as reference register values; and; and correcting register values of remaining m−s binding points based on the reference Gamma register values and the target Gamma curve to obtain a set of target Gamma register values corresponding to the m binding points, wherein s, m and x are all integers greater than one.
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公开(公告)号：US10984692B2
公开(公告)日：2021-04-20
申请号：US16056476
申请日：2018-08-06
Inventor： Dexiong Song , Zhiyong Yang , Shihua Huang , Wei He , Jing Wang , Liwei Huang , Xue Jiang , Wei Li , Chao Fu
IPC: G09G3/00 , G09G3/3258 , G09G3/20
Abstract: A test display panel is configured for application to a lighting test, and includes a plurality of reference voltage input terminals and a plurality of sub-pixels. The reference voltage input terminals are in a one-to-one correspondence to the sub-pixels. The display panel further includes a reference voltage supply circuit and a plurality of reference voltage lines. The sub-pixels include a plurality of first sub-pixels, second sub-pixels, and third sub-pixels having different colors. The reference voltage lines include a first reference voltage line, a second reference voltage line, and a third reference voltage line, each corresponding to respective sub-pixels. The reference voltage supply circuit is configured to provide reference voltages to the plurality of reference voltage lines in a time division manner. The reference voltage lines are electrically coupled to respective reference voltage input terminals of the sub-pixels.
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公开(公告)号：US09721521B2
公开(公告)日：2017-08-01
申请号：US15398624
申请日：2017-01-04
Inventor： Xue Jiang , Xinghua Li , Wei He
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3681 , G09G2310/0213 , G09G2310/08 , G09G2330/021
Abstract: The present disclosure discloses a gate driving method, a driving apparatus of a display panel and a display apparatus. The driving apparatus may be in two driving modes, i.e., a first mode and a second mode. In the first mode, due to a reduced number of gate lines to be driven when various frames of images are displayed, the power consumption can be reduced. In addition, due to the effect of persistence of vision of human eyes, better quality of display images can be ensured while reducing power consumption. In the second mode, as respective lines of gate lines are driven progressively when various frames of images are displayed, the display panel is enabled to have better quality of display images. By switching the driving apparatus between the first mode and second mode, a number of gate lines to be driven can be reduced so as to reduce power consumption.
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10.发明授权公开(公告)号：US12249524B2
公开(公告)日：2025-03-11
申请号：US17264902
申请日：2020-05-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yang Yue , Tong Yang , Shi Shu , Yong Yu , Haitao Huang , Xiang Li , Qi Yao , Xue Jiang , Guangcai Yuan
IPC: H01L21/67 , B65G47/90 , H01L25/075 , H01L33/62 , H10N30/00 , H10N30/074 , H10N30/20 , H10N39/00
Abstract: Provided in the embodiments are a transfer structure and a method thereof, and a transfer device and a manufacturing method thereof. The transfer structure includes: a first electrode, a piezoelectric layer, a second electrode and an adhesive layer stacked on a substrate in sequence, wherein the first electrode and the second electrode are insulated from each other. The transfer structure further includes: a position-limiting layer, wherein the position-limiting layer includes a cavity; the piezoelectric layer and at least part of the adhesive layer are located in the cavity of the position-limiting layer; and in the direction perpendicular to the substrate, the distance between the surface, away from the substrate, of the position-limiting layer and the substrate is greater than the distance between the surface, away from the substrate, of the adhesive layer and the substrate.
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