Interlaced counting circuits
    1.
    发明授权
    Interlaced counting circuits 失效
    互连计数电路

    公开(公告)号:US3618036A

    公开(公告)日:1971-11-02

    申请号:US3618036D

    申请日:1968-12-18

    Inventor: CARBREY ROBERT L

    CPC classification number: H04L25/03038

    Abstract: A circuit is described for coordinating the addressing of a plurality of tap multipliers in a transversal filter, which is employed as a pre-equalizer. with a received data stream. The data stream updates information stored in a memory. The updated information is applied to the tap multipliers at a rate eight times the rate that the data stream updates the memory. A memory and tap address counter, operating at a rate that the information is applied to the taps is synchronized with the updating data stream by causing the address counter to slip one count for each cycle thereof.

    Capacitive switched gain ratio operational amplifier pcm decoder
    10.
    发明授权
    Capacitive switched gain ratio operational amplifier pcm decoder 失效
    电容开关增益比运算放大器PCM解码器

    公开(公告)号:US3651515A

    公开(公告)日:1972-03-21

    申请号:US3651515D

    申请日:1969-11-25

    Inventor: CARBREY ROBERT L

    CPC classification number: H03M1/124

    Abstract: A self-companding pulse code modulation converter employs switched gain ratio of an operational amplifier. Capacitors, weighted to correspond to the quantizing characteristic, are switched between the input and feedback circuits of an operational amplifier to change the gain ratio.

    Abstract translation: 自分压脉冲编码调制转换器采用运算放大器的开关增益比。 加权以对应于量化特性的电容器在运算放大器的输入和反馈电路之间切换以改变增益比。

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