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公开(公告)号：US08207770B1
公开(公告)日：2012-06-26
申请号：US12978394
申请日：2010-12-23
申请人： Ashoke Ravi , Pin-En Su , Paolo Madoglio , Georgios Palaskas
发明人： Ashoke Ravi , Pin-En Su , Paolo Madoglio , Georgios Palaskas
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/1976 , H03L2207/50
摘要： An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.
摘要翻译： 装置可以包括时间到数字电路架构。 描述和要求保护其他实施例。
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公开(公告)号：US20120161831A1
公开(公告)日：2012-06-28
申请号：US12978394
申请日：2010-12-23
申请人： Ashoke Ravi , Pin-En Su , Paolo Madoglio , Georgios Palaskas
发明人： Ashoke Ravi , Pin-En Su , Paolo Madoglio , Georgios Palaskas
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/1976 , H03L2207/50
摘要： An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.
摘要翻译： 装置可以包括时间到数字电路架构。 描述和要求保护其他实施例。
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3.发明授权System, method and apparatus for an open loop calibrated phase wrapping phase modulator for wideband RF outphasing/polar transmitters 有权用于宽带RF外相/极性发射机的开环校准相位缠绕相位调制器的系统，方法和装置公开(公告)号：US08222966B2
公开(公告)日：2012-07-17
申请号：US12879152
申请日：2010-09-10
摘要： A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.
摘要翻译： 用于开环校准相位缠绕相位调制器的器件制品和方法。 抽头延迟线可以为信号的一个或多个相位提供粗分辨率。 相位多路复用器可以从抽头延迟线接收一个或多个粗略相位，并选择粗略相位以发送到数字控制的延迟线。 数字控制的延迟线可以从相位多路复用器提供到粗略相位的精细分辨率。
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4.发明申请SYSTEM, METHOD AND APPARATUS FOR AN OPEN LOOP CALIBRATED PHASE WRAPPING PHASE MODULATOR FOR WIDEBAND RF OUTPHASING/POLAR TRANSMITTERS 有权用于宽带射频输出/极性发射器的开环校准相位调制器的系统，方法和装置公开(公告)号：US20120062331A1
公开(公告)日：2012-03-15
申请号：US12879152
申请日：2010-09-10
IPC分类号： H03C3/02
摘要： A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.
摘要翻译： 用于开环校准相位缠绕相位调制器的器件制品和方法。 抽头延迟线可以为信号的一个或多个相位提供粗分辨率。 相位多路复用器可以从抽头延迟线接收一个或多个粗略相位，并选择粗略相位以发送到数字控制的延迟线。 数字控制的延迟线可以从相位多路复用器提供到粗略相位的精细分辨率。
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公开(公告)号：US20150181643A1
公开(公告)日：2015-06-25
申请号：US14138508
申请日：2013-12-23
申请人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
发明人： Hasnain Lakdawala , Ashoke Ravi , Ofir Degani , Bernd-Ulrich Klepser , Zdravko Boos , Georgios Palaskas , Stefano Pellerano , Paolo Madoglio
CPC分类号： H04L7/033 , H03K2005/00234 , H03L7/16 , H04B7/0413 , H04B7/06 , H04L27/152 , H04L27/1525 , H04L27/20 , H04W88/06
摘要： This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
摘要翻译： 本应用程序还讨论了用于在多个无线设备之间共享本地振荡器的装置和方法。 在某些示例中，装置可以包括配置成提供具有第一频率的中心振荡器信号的中央频率合成器，第一发射机，第一发射机包括被配置为接收中心振荡器的第一发射数字 - 时间转换器（DTC） 并且提供具有第二频率的第一发射机信号和第一接收机，所述第一接收机包括被配置为接收中心振荡器信号并提供具有第一接收频率的第一接收机信号的第一接收DTC。
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公开(公告)号：US07657232B2
公开(公告)日：2010-02-02
申请号：US11522599
申请日：2006-09-18
CPC分类号： H03F1/32 , H03F1/34 , H03F3/24 , H03F2200/321 , H03F2200/451 , H04B2001/0433
摘要： Embodiments of methods and means for calibrating a linearization characteristic within an RF transceiver system are provided. Such embodiments generally include extracting a portion of an output signal and frequency shifting or translating that signal by a predetermined value. The frequency shifted signal is then summed or otherwise introduced into a receiver signal pathway where it is analyzed by digital signal processing or other means to determine if linearization distortion is present. Linearization calibration of a power amplifier, a low-noise amplifier and/or other functionality within the system can then be performed in an automatic, reliable and ongoing manner.
摘要翻译： 提供了用于校准RF收发器系统内的线性化特性的方法和装置的实施例。 这样的实施例通常包括提取输出信号的一部分并将该信号频移或转换预定值。 然后将频移信号相加或以其他方式引入到接收机信号路径中，其中通过数字信号处理或其他手段来分析，以确定是否存在线性化失真。 然后可以以自动，可靠和持续的方式执行系统内的功率放大器，低噪声放大器和/或其他功能的线性化校准。
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7.发明授权Multiple-input multiple-output multichip transceiver with correlated clock signals 失效具有相关时钟信号的多输入多输出多芯片收发器公开(公告)号：US07609792B2
公开(公告)日：2009-10-27
申请号：US11069172
申请日：2005-03-01
申请人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
发明人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard B. Nicholls , Keith A. Holt , Stanley K. Ling
IPC分类号： H04B7/10
CPC分类号： H04L1/06
摘要： A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.
摘要翻译： 多芯片收发器作为多输入多输出通信系统的一部分而工作。 第一集成电路上的第一接收器电路处理从第一信号源接收的射频（RF）信号，第二集成电路上的第二接收器电路处理从第二信号源接收的RF信号。 时钟信号产生电路通过相位匹配的路径提供时钟信号到第一和第二接收器电路。
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8.发明申请Transceiver with calibrated I and Q paths and methods for deconvolved calibration 有权具有校准I和Q路径的收发器以及用于去卷积校准的方法公开(公告)号：US20050220003A1
公开(公告)日：2005-10-06
申请号：US10815138
申请日：2004-03-31
申请人： Georgios Palaskas , Ashoke Ravi , Jeyanandh Paramesh , Richard Nicholls , Krishnamurthy Soumyanath
发明人： Georgios Palaskas , Ashoke Ravi , Jeyanandh Paramesh , Richard Nicholls , Krishnamurthy Soumyanath
摘要： Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.
摘要翻译： 可以通过在接收机校准信号上执行快速傅立叶变换（FFT）来测量接收机射频（RF）电路的接收机幅度和相位失配来减少多载波收发器的相位和幅度偏移。
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公开(公告)号：US07212141B2
公开(公告)日：2007-05-01
申请号：US11178625
申请日：2005-07-11
申请人： Hasnain Lakdawala , Ashoke Ravi , Georgios Palaskas , Stefan H. Andersson , Krishnamurthy Soumyanath
发明人： Hasnain Lakdawala , Ashoke Ravi , Georgios Palaskas , Stefan H. Andersson , Krishnamurthy Soumyanath
CPC分类号： H03H15/02
摘要： Embodiments of a filter with gain are presented herein.
摘要翻译： 本文给出了具有增益的滤波器的实施例。
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10.发明申请Multiple-input multiple-output multichip transceiver with correlated clokc signals 失效具有相关clokc信号的多输入多输出多芯片收发器公开(公告)号：US20060198476A1
公开(公告)日：2006-09-07
申请号：US11069172
申请日：2005-03-01
申请人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard Nicholls , Keith Holt , Stanley Ling
发明人： Georgios Palaskas , Ashoke Ravi , Soumyanath Krishnamurthy , Richard Nicholls , Keith Holt , Stanley Ling
IPC分类号： H04L1/02
CPC分类号： H04L1/06
摘要： A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.
摘要翻译： 多芯片收发器作为多输入多输出通信系统的一部分而工作。 第一集成电路上的第一接收器电路处理从第一信号源接收的射频（RF）信号，第二集成电路上的第二接收器电路处理从第二信号源接收的RF信号。 时钟信号产生电路通过相位匹配的路径提供时钟信号到第一和第二接收器电路。
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