公开(公告)号：US20240290883A1

公开(公告)日：2024-08-29

申请号：US18441808

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Hui Zhao ,  Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu

IPC: H01L29/78 ,  H01L21/762 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

公开(公告)号：US20200251151A1

公开(公告)日：2020-08-06

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H01L27/108

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US12183631B2

公开(公告)日：2024-12-31

申请号：US17839817

申请日：2022-06-14

Applicant: Applied Materials, Inc.

Inventor： Suketu Parikh ,  Alexander Jansen ,  Joung Joo Lee ,  Lequn Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/532

Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

公开(公告)号：US20240160100A1

公开(公告)日：2024-05-16

申请号：US18222897

申请日：2023-07-17

Applicant: Applied Materials, Inc.

Inventor： Tzu Shun Yang ,  Zhenxing Han ,  Madhur Sachan ,  Lequn Liu ,  Nasrin Kazem ,  Lakmal Charidu Kalutarage ,  Mark Joseph Saly

IPC: G03F7/004 ,  G03F7/00 ,  G03F7/16 ,  G03F7/36 ,  H01L21/027

CPC classification number: G03F7/0042 ,  G03F7/167 ,  G03F7/36 ,  G03F7/70033 ,  H01L21/0274

Abstract: Embodiments disclosed herein may include a method for developing a photopatterned metal oxo photoresist. In an embodiment, the method may include pre-treating the photopatterned metal oxo photoresist with a pre-treatment process, developing the photopatterned metal oxo photoresist with a thermal dry develop process to selectively remove a portion of the photopatterned metal oxo photoresist and form a resist mask. In an embodiment, the thermal dry develop process includes a first sub-operation, and a second sub-operation that is different than the first sub-operation. In an embodiment, the process further includes post-treating the resist mask with a post-treatment process.

公开(公告)号：US20240071773A1

公开(公告)日：2024-02-29

申请号：US18232916

申请日：2023-08-11

Applicant: Applied Materials, Inc.

Inventor： Lei Liao ,  Yichuan Ling ,  Zhiyu Huang ,  Hideyuki Kanzawa ,  Fenglin Wang ,  Rajesh Prasad ,  Yung-Chen Lin ,  Chi-I Lang ,  Ho-yung David Hwang ,  Lequn Liu

IPC: H01L21/3115 ,  H01L21/02

CPC classification number: H01L21/31155 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

公开(公告)号：US20240038553A1

公开(公告)日：2024-02-01

申请号：US18225799

申请日：2023-07-25

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Lequn Liu ,  Brian K. Kirkpatrick

IPC: H01L21/67 ,  H01L29/66

CPC classification number: H01L21/67069 ,  H01L29/66545 ,  H01L21/67075 ,  H01L21/67167 ,  H01L21/67207 ,  H01L29/66439 ,  H01L29/0673

Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.

公开(公告)号：US20220238533A1

公开(公告)日：2022-07-28

申请号：US17717582

申请日：2022-04-11

Applicant: Applied Materials, Inc.

Inventor： Lequn Liu ,  Priyadarshi Panda ,  Jonathan C. Shaw

IPC: H01L27/108 ,  H01L21/67

Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

公开(公告)号：US11295786B2

公开(公告)日：2022-04-05

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: H01L27/108 ,  H01L21/8242 ,  G11C5/06

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US11751382B2

公开(公告)日：2023-09-05

申请号：US17717582

申请日：2022-04-11

Applicant: Applied Materials, Inc.

Inventor： Lequn Liu ,  Priyadarshi Panda ,  Jonathan C. Shaw

IPC: H01L21/67 ,  H10B12/00

CPC classification number: H10B12/482 ,  H01L21/67167 ,  H01L21/67213

Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

公开(公告)号：US11749315B2

公开(公告)日：2023-09-05

申请号：US17551538

申请日：2021-12-15

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: G11C5/06 ,  H10B12/00

CPC classification number: G11C5/063 ,  H10B12/02 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/30 ,  H10B12/318 ,  H10B12/482 ,  H10B12/488

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.