公开(公告)号：US10592367B2

公开(公告)日：2020-03-17

申请号：US15939089

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Steven Frederick Schicht ,  William R. Weier

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G11C7/10 ,  G11C29/00 ,  G11C11/419 ,  G11C29/12

Abstract: Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

公开(公告)号：US10535400B2

公开(公告)日：2020-01-14

申请号：US15939078

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： William R. Weier ,  Steven Frederick Schicht

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

公开(公告)号：US09564901B1

公开(公告)日：2017-02-07

申请号：US14972754

申请日：2015-12-17

Applicant: Apple Inc.

Inventor： Daniel C. Chow ,  Kenneth W. Jones ,  William R. Weier

IPC: H03K19/0185 ,  H03K3/356 ,  H03K5/156

CPC classification number: H03K19/01855 ,  H03K5/05 ,  H03K5/1565

Abstract: A clock circuit configured to generate a falling edge independently of an input clock signal is disclosed. In one embodiment, a clock circuit includes an input circuit coupled to receive an input clock signal. A corresponding first clock signal is provided on a first clock node, while a second clock signal that is a delayed version of the first is provided on a second clock signal. The clock circuit may generate an output clock signal based on the first and second clock signals and a feedback signal received from a functional circuit coupled to receive the output clock signal. The rising edge of the output clock signal is generated dependent upon when the rising edge of the input clock signal is received. The falling edge of the output clock signal is generated by the clock circuit independently of when the falling edge of the input clock signal is received.

Abstract translation: 公开了一种配置成独立于输入时钟信号产生下降沿的时钟电路。 在一个实施例中，时钟电路包括耦合以接收输入时钟信号的输入电路。 在第一时钟节点上提供对应的第一时钟信号，而在第二时钟信号上提供作为第一时钟信号的延迟版本的第二时钟信号。 时钟电路可以基于第一和第二时钟信号产生输出时钟信号，以及从耦合以接收输出时钟信号的功能电路接收的反馈信号。 输出时钟信号的上升沿取决于输入时钟信号的上升沿何时被接收。 输出时钟信号的下降沿由时钟电路产生，独立于接收到输入时钟信号的下降沿时。

公开(公告)号：US11038492B2

公开(公告)日：2021-06-15

申请号：US16544591

申请日：2019-08-19

Applicant: Apple Inc.

Inventor： Steven F. Schicht ,  William R. Weier

IPC: G05F1/04 ,  H03K3/00 ,  H03K3/027 ,  H03K19/17736 ,  H03K19/00 ,  H03K3/017

Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

公开(公告)号：US10389335B1

公开(公告)日：2019-08-20

申请号：US15970986

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Steven F. Schicht ,  William R. Weier

IPC: G06F1/04 ,  H03K3/027 ,  H03K19/177 ,  H03K19/00 ,  H03K3/017

Abstract: In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.

公开(公告)号：US20190087291A1

公开(公告)日：2019-03-21

申请号：US15939089

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Steven Frederick Schicht ,  William R. Weier

IPC: G06F11/20 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

公开(公告)号：US20190080748A1

公开(公告)日：2019-03-14

申请号：US15939078

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： William R. Weier ,  Steven Frederick Schicht

IPC: G11C11/419 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/22 ,  G11C29/702 ,  G11C29/74

Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

公开(公告)号：US09922688B2

公开(公告)日：2018-03-20

申请号：US15242734

申请日：2016-08-22

Applicant: Apple Inc.

Inventor： William R. Weier

IPC: G11C7/10 ,  H01L29/78 ,  H03K19/20 ,  H03K3/356 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/106 ,  G11C11/419 ,  H01L29/785 ,  H03K19/20

Abstract: A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using a single pair of transistors that are cross-coupled between first and second differential signal nodes. A gate terminal of a first one of the pair of transistors is coupled to the first differential signal node, while the drain terminal of the same transistor is coupled to the second differential signal node. The gate terminal of a second one of the pair of transistors is coupled to the second differential signal node, while its drain terminal is coupled to the first differential signal node. The bitline sensing latch also includes a precharge circuit, and may operates in two phases, a precharge phase and an enable phase.

公开(公告)号：US20180053536A1

公开(公告)日：2018-02-22

申请号：US15242734

申请日：2016-08-22

Applicant: Apple Inc.

Inventor： William R. Weier

IPC: G11C7/10 ,  H01L29/78 ,  H03K19/20 ,  H03K3/356 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/106 ,  G11C11/419 ,  H01L29/785 ,  H03K19/20

Abstract: A bit line sensing latch circuit is disclosed. In one embodiment, a latch circuit includes a keeper and a precharge circuit. The keeper may be implemented using a single pair of transistors that are cross-coupled between first and second differential signal nodes. A gate terminal of a first one of the pair of transistors is coupled to the first differential signal node, while the drain terminal of the same transistor is coupled to the second differential signal node. The gate terminal of a second one of the pair of transistors is coupled to the second differential signal node, while its drain terminal is coupled to the first differential signal node. The bitline sensing latch also includes a precharge circuit, and may operates in two phases, a precharge phase and an enable phase.