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49 条记录 (耗时 0.02 秒)

    Structure for integrated touch screen
    3.
    发明授权
    Structure for integrated touch screen 有权

    公开(公告)号：US10133382B2

    公开(公告)日：2018-11-20

    申请号：US15311836

    申请日：2014-10-02

    申请人： Apple Inc.

    发明人： Byung Duk Yang ,  Kyung Wook Kim ,  Szu-Hsien Lee ,  Shih-Chang Chang ,  John Z. Zhong

    IPC分类号： G06F3/041 ,  G06F3/044 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362

    摘要： A touch screen is disclosed. The touch screen can comprise a substrate having a first surface upon which a touch or proximity event is to be detected, and a second surface that opposes the first surface, and a touch sensor electrode and a first display pixel including a first display pixel TFT formed on the second surface of the substrate. The first touch sensor electrode can be disposed between the second surface of the substrate and the first display pixel TFT, and the first touch sensor electrode can be configured to detect the touch or proximity event. In some examples, the substrate can comprise a TFT glass substrate. In some examples, the touch screen can comprise a first touch sensor routing electrically coupled to the first touch sensor electrode, wherein the first touch sensor routing is disposed between the second surface of the substrate and the first display pixel TFT.

    Displays with intra-frame pause
    4.
    发明授权
    Displays with intra-frame pause 有权
    显示帧内暂停

    公开(公告)号：US09557840B2

    公开(公告)日：2017-01-31

    申请号：US14489338

    申请日：2014-09-17

    申请人： Apple Inc.

    发明人： Chin-Wei Lin ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC分类号： G06F3/041

    CPC分类号： G06F3/0412 ,  G06F3/0416

    摘要： A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.

    摘要翻译： 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。

    Displays with Circuitry for Compensating Parasitic Coupling Effects
    6.
    发明申请
    Displays with Circuitry for Compensating Parasitic Coupling Effects 审中-公开
    显示带补偿寄生耦合效应的电路

    公开(公告)号：US20140111496A1

    公开(公告)日：2014-04-24

    申请号：US13657763

    申请日：2012-10-22

    申请人： APPLE INC.

    发明人： Jason N. Gomez ,  Kyung-Wook Kim ,  Szu-Hsien Lee

    IPC分类号： G06F3/038 ,  G09G3/36

    CPC分类号： G09G3/3696 ,  G09G2320/0214 ,  G09G2320/0219

    摘要： An electronic device may have a display such as a liquid crystal display. The display may have a color filter layer and a thin-film transistor (TFT) layer. An active portion of the display may contain an array of display pixels that are controlled by control signals that are provided over intersecting gate lines and data lines. In an inactive portion of the display, display driver circuitry may be used to provide data signals for the data lines. Each display pixel may be coupled to a corresponding gate line, data line, and may share a common electrode. Changes in the data signals may be coupled onto the common electrode to cause voltage rippling. Compensation circuitry may be coupled to the common electrode via an AC or a DC coupling connection to help reduce the voltage rippling.

    摘要翻译： 电子设备可以具有诸如液晶显示器的显示器。 显示器可以具有滤色器层和薄膜晶体管（TFT）层。 显示器的有效部分可以包含由在相交的栅极线和数据线上提供的控制信号控制的显示像素阵列。 在显示器的非活动部分中，显示驱动器电路可用于为数据线提供数据信号。 每个显示像素可以耦合到对应的栅极线，数据线，并且可以共享公共电极。 可以将数据信号的变化耦合到公共电极上以引起电压波动。 补偿电路可以经由AC或DC耦合连接耦合到公共电极，以帮助减小电压波动。

    Pixel array antialiasing to accommodate curved display edges
    7.
    发明授权
    Pixel array antialiasing to accommodate curved display edges 有权

    公开(公告)号：US10409118B1

    公开(公告)日：2019-09-10

    申请号：US15498356

    申请日：2017-04-26

    申请人： Apple Inc.

    发明人： Pei-En Chang ,  Szu-Hsien Lee ,  Hsin-Ying Chiu ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Hossein Nemati

    IPC分类号： G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  H01L27/32 ,  G02F1/133

    摘要： An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The pixels may be organic light-emitting diode pixels, liquid crystal display pixels, or other display pixels. Organic light-emitting diode pixels may have drive transistors and associated organic light-emitting diodes. Selectively elevated series or opaque light blocking structures of selectively reduced areas may be used to selectively reduce the strength of the antialiasing pixels. Liquid crystal display pixels may include electrodes of different shapes and/or opaque layer openings of different sizes to form antialiasing pixels in desired patterns.

    Multi-zoned variable VCOM control
    8.
    发明授权
    Multi-zoned variable VCOM control 有权

    公开(公告)号：US10380937B2

    公开(公告)日：2019-08-13

    申请号：US15246666

    申请日：2016-08-25

    申请人： Apple Inc.

    发明人： Howard H. Tang ,  Paolo Sacchetto ,  Chaohao Wang ,  Szu-Hsien Lee ,  Patrick Bennett ,  Fenghua Zheng

    IPC分类号： G09G3/20 ,  G09G3/36

    摘要： The disclosure relates to systems and methods for reducing VCOM settling periods. A number of pixels is sub-divided into a plurality of regions. The pixels are configured to transmit light. A common voltage (VCOM) driving circuit is configured to drive a common electrode of the pixels. Moreover, each of a number of VCOM driving circuits includes a variable resistor configured to be driven to a resistance level based at least in part on which region of the plurality of regions includes an active pixel within the region. Furthermore, a resistance level is set and based at least in part on where the active pixel is located.

    Display gate driver circuits with dual pulldown transistors
    9.
    发明授权
    Display gate driver circuits with dual pulldown transistors 有权

    公开(公告)号：US10037738B2

    公开(公告)日：2018-07-31

    申请号：US14862071

    申请日：2015-09-22

    申请人： Apple Inc.

    发明人： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC分类号： G09G3/36 ,  G09G3/3225 ,  G09G3/20

    CPC分类号： G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

    摘要： A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.