知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.036 seconds)

    ALTERNATE-LOGIC HEAD-TO-HEAD GATE DRIVER ON ARRAY
    3.
    发明申请
    ALTERNATE-LOGIC HEAD-TO-HEAD GATE DRIVER ON ARRAY 审中-公开

    公开(公告)号：US20200074912A1

    公开(公告)日：2020-03-05

    申请号：US16234127

    申请日：2018-12-27

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Szu-Hsien Lee

    IPC: G09G3/20 ,  G09G3/3266 ,  G09G3/36

    Abstract: The disclosure is related to head-to-head (H2H) gate on arrays (GOA) for pixel-based displays that may have reduced dimensions. In the described embodiments, the H2H design with alternate logic may be used to drive groups of pixels (e.g., a pixel row or column) with a primary and a secondary driver, located in opposite ends of the bezel of the electronic device. In the alternate-logic design, a shared shift-register may be used to enable two rows or columns. Embodiments in which more than two rows or columns are controlled by a single shift register are also described.

    Display with driver circuitry having intraframe pause capabilities
    4.
    发明授权
    Display with driver circuitry having intraframe pause capabilities 有权

    公开(公告)号：US09727165B2

    公开(公告)日：2017-08-08

    申请号：US14677531

    申请日：2015-04-02

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G06F3/041 ,  G09G3/36

    CPC classification number: G06F3/0416 ,  G09G3/3677 ,  G09G2310/0202 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2320/043

    Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

    RC tuning of touch electrode connections on a touch sensor panel
    6.
    发明授权
    RC tuning of touch electrode connections on a touch sensor panel 有权

    公开(公告)号：US10955947B2

    公开(公告)日：2021-03-23

    申请号：US15493791

    申请日：2017-04-21

    Applicant: Apple Inc.

    Inventor： Patrick Bennett ,  Byung Duk Yang ,  Chun-Yao Huang ,  Hao-Lin Chiu ,  Ivan Knez ,  Peien Chang ,  Rungrot Kitsomboonloha ,  Shih-Chang Chang ,  Shinya Ono ,  Szuhsien Lee

    IPC: G06F3/041 ,  G06F3/044

    Abstract: A touch sensor panel comprising a first touch node electrode of a plurality of touch node electrodes, the first touch node electrode coupled to a first sense connection comprising a first set of traces, the first sense connection configured to have a first resistance per unit length that varies along a length of the first sense connection, and a second touch node electrode of the plurality of touch node electrodes, the second touch node electrode coupled to a second sense connection comprising a second set of traces, the second sense connection configured to have a second resistance per unit length that varies along a length of the second sense connection differently than the first resistance per unit length varies along the length of the first sense connection. An effective resistance of the first sense connection and the second sense connection are equal.

    Display gate driver circuits with dual pulldown transistors
    7.
    发明授权
    Display gate driver circuits with dual pulldown transistors 有权

    公开(公告)号：US10037738B2

    公开(公告)日：2018-07-31

    申请号：US14862071

    申请日：2015-09-22

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G09G3/36 ,  G09G3/3225 ,  G09G3/20

    CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

    Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

    Display Gate Driver Circuits with Dual Pulldown Transistors
    8.
    发明申请
    Display Gate Driver Circuits with Dual Pulldown Transistors 审中-公开
    显示具有双下拉晶体管的栅极驱动器电路

    公开(公告)号：US20170004790A1

    公开(公告)日：2017-01-05

    申请号：US14862071

    申请日：2015-09-22

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Kyung Wook Kim ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G09G3/36 ,  G09G3/32

    CPC classification number: G09G3/3674 ,  G09G3/20 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291

    Abstract: A display is provided that includes an array of display pixels and gate driver circuitry for providing data and gate line signals to the display pixels. Gate driver circuitry may include gate driver circuits that generate the gate line signals. A gate driver circuit may include at least a buffer transistor, a bootstrapping capacitor coupled to the buffer transistor, a pulldown transistor coupled in series with the buffer transistor, and an isolation transistor coupled to the gate of the pulldown transistor. The buffer transistor may directly receive a first clock signal, whereas the isolation transistor may directly receive a second clock signal that is complementary to the first clock signal. The pulldown transistor is substantially larger than the buffer transistor. The buffer transistor is substantially larger than the isolation transistor. Configured as such, clock loading is minimized while the pulldown transistor is sized to provide the desired fall time performance.

    Abstract translation: 提供了一种显示器，其包括用于向显示像素提供数据和栅极线信号的显示像素阵列和栅极驱动器电路。 栅极驱动器电路可以包括产生栅极线信号的栅极驱动器电路。 栅极驱动器电路可以包括至少缓冲晶体管，耦合到缓冲晶体管的自举电容器，与缓冲晶体管串联耦合的下拉晶体管，以及耦合到下拉晶体管的栅极的隔离晶体管。 缓冲晶体管可以直接接收第一时钟信号，而隔离晶体管可以直接接收与第一时钟信号互补的第二时钟信号。 下拉晶体管实质上大于缓冲晶体管。 缓冲晶体管基本上大于隔离晶体管。 如此配置，时钟负载最小化，而下拉晶体管的尺寸设置为提供所需的下降时间性能。

    Display With Driver Circuitry Having Intraframe Pause Capabilities
    9.
    发明申请
    Display With Driver Circuitry Having Intraframe Pause Capabilities 有权
    显示具有内部帧暂停功能的驱动器电路

    公开(公告)号：US20160293081A1

    公开(公告)日：2016-10-06

    申请号：US14677531

    申请日：2015-04-02

    Applicant: Apple Inc.

    Inventor： Rungrot Kitsomboonloha ,  Chun-Yao Huang ,  Shih Chang Chang ,  Szu-Hsien Lee

    IPC: G09G3/20 ,  G06F3/044 ,  G06F3/042 ,  G06F3/041

    CPC classification number: G06F3/0416 ,  G09G3/3677 ,  G09G2310/0202 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2320/043

    Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include blocks of gate driver circuits each having an output coupled to a respective one of the gate lines. The gate driver circuits of each block are coupled in a chain to form a shift register. Each block has a local block-level gate start pulse generator. The display driver circuitry has a display driver circuit that supplies a gate start pulse clock to each of the local block-level gate start pulse generators. The local block-level gate start pulse generators create gate start pulses that are applied to the first gate driver circuit in each shift register. The display driver circuit may delay the gate start pulse clock when it is desired to implement an intraframe pause.

    Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器电路块，每个栅极驱动器电路具有耦合到相应的一条栅极线的输出。 每个块的栅极驱动器电路被耦合在链中以形成移位寄存器。 每个块具有本地块级门控起始脉冲发生器。 显示驱动器电路具有显示驱动器电路，其向每个本地块级门控起始脉冲发生器提供栅极起始脉冲时钟。 局部块电平门起始脉冲发生器产生施加到每个移位寄存器中的第一栅极驱动器电路的栅极起始脉冲。 当期望实现帧内暂停时，显示驱动器电路可以延迟门启动脉冲时钟。

Patent Agency Ranking