公开(公告)号：US11887546B2

公开(公告)日：2024-01-30

申请号：US18192905

申请日：2023-03-30

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L29/786 ,  H10K59/121

CPC classification number: G09G3/3258 ,  H01L29/7869 ,  H10K59/1213 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US11508309B2

公开(公告)日：2022-11-22

申请号：US17317128

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

公开(公告)号：US11348533B1

公开(公告)日：2022-05-31

申请号：US16864241

申请日：2020-05-01

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Gihoon Choo ,  Shiping Shen ,  Jie Won Ryu ,  Zino Lee ,  Hassan Edrees ,  Ting-Kuo Chang

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.

公开(公告)号：US20200226978A1

公开(公告)日：2020-07-16

申请号：US16716911

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US20250037672A1

公开(公告)日：2025-01-30

申请号：US18919947

申请日：2024-10-18

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Zino Lee ,  Chun-Chieh Lin ,  Chen-Ming Chen

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

公开(公告)号：US20230237965A1

公开(公告)日：2023-07-27

申请号：US18192905

申请日：2023-03-30

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L29/786 ,  H10K59/121

CPC classification number: G09G3/3258 ,  H01L29/7869 ,  H10K59/1213 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US20230042963A1

公开(公告)日：2023-02-09

申请号：US17970842

申请日：2022-10-21

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

公开(公告)号：US20220180819A1

公开(公告)日：2022-06-09

申请号：US17501530

申请日：2021-10-14

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Zino Lee ,  Chun-Chieh Lin ,  Chen-Ming Chen

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

公开(公告)号：US20220180812A1

公开(公告)日：2022-06-09

申请号：US17680059

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US11049457B1

公开(公告)日：2021-06-29

申请号：US16852234

申请日：2020-04-17

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Chun-Chieh Lin ,  Gihoon Choo ,  Hassan Edrees ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.