公开(公告)号：US11054882B2

公开(公告)日：2021-07-06

申请号：US16281283

申请日：2019-02-21

Applicant: Apple Inc.

Inventor： Daniel U. Becker

IPC: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F7/58

Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

公开(公告)号：US10969858B2

公开(公告)日：2021-04-06

申请号：US16238984

申请日：2019-01-03

Applicant: Apple Inc.

Inventor： Daniel U. Becker ,  Aditya Kesiraju ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Boris S. Alvarez-Heredia

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/329

Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

公开(公告)号：US20200272217A1

公开(公告)日：2020-08-27

申请号：US16281283

申请日：2019-02-21

Applicant: Apple Inc.

Inventor： Daniel U. Becker

IPC: G06F1/3234

Abstract: In an embodiment, a local throttling mechanism for the one or more processor cores may support one or more externally-triggered throttling mechanisms. An external source, such as a system-level power manager, may detect an energy-consumption state in the system as a whole and may trigger additional throttling in the processor core throttling mechanism. The externally-triggered throttling may temporarily increase throttling in the processor cores, in an embodiment, decreasing processor core energy consumption to account for the excess energy consumption in other parts of the system.

公开(公告)号：US20200218327A1

公开(公告)日：2020-07-09

申请号：US16238984

申请日：2019-01-03

Applicant: Apple Inc.

Inventor： Daniel U. Becker ,  Aditya Kesiraju ,  Srikanth Balasubramanian ,  Venkatram Krishnaswamy ,  Boris S. Alvarez-Heredia

IPC: G06F1/329

Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.

公开(公告)号：US09928115B2

公开(公告)日：2018-03-27

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, Jr. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F12/084 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0813

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

公开(公告)号：US20250044844A1

公开(公告)日：2025-02-06

申请号：US18365783

申请日：2023-08-04

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Alexander Gendler ,  Daniel U. Becker ,  Saher Odeh ,  Ilya Granovsky ,  Lior Zimet

IPC: G06F1/26

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

公开(公告)号：US11281279B2

公开(公告)日：2022-03-22

申请号：US16373461

申请日：2019-04-02

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Daniel U. Becker ,  Achmed R. Zahir

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3296

Abstract: An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.

公开(公告)号：US20170068575A1

公开(公告)日：2017-03-09

申请号：US14844212

申请日：2015-09-03

Applicant: Apple Inc.

Inventor： James N. Hardage, JR. ,  Daniel U. Becker ,  Christopher M. Tsay ,  Richard F. Russo ,  Shih-Chieh R. Wen ,  Richard H. Larson

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/5088 ,  G06F9/30101 ,  G06F9/3828 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 处理器可以支持多种处理器状态（PState）。 每个PState可以指定工作点（例如，电源电压幅度和时钟频率的组合），并且每个PState可以映射到处理器核心之一。 在运行期间，其中一个核心是活动的：当前PState映射到的核心。 如果选择新的PState并将其映射到不同的核心，则处理器可以自动地将处理器状态切换到新选择的核心，并且可以在该核心上开始执行。 可以使用专用寄存器（SPR）互连来执行上下文切换。 给定处理器中的每个处理器核心可以耦合到SPR互连以允许访问外部SPR。

公开(公告)号：US20160077136A1

公开(公告)日：2016-03-17

申请号：US14487472

申请日：2014-09-16

Applicant: Apple Inc.

Inventor： Daniel U. Becker ,  Cyril de la Cropte de Chanterac

IPC: G01R21/00 ,  G01R31/28

CPC classification number: G06F1/3203 ,  G06F1/3212 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/174 ,  Y02D10/24

Abstract: Embodiments of a computing system that may monitor energy usage are disclosed. The embodiments may provide a low overhead method for determining energy usage of a given application or process. Circuitry is configured to determine a respective energy for each of the plurality of operations and sum each respective energy for at least some of the plurality of operations to generate a normalized total. The circuitry may be further configured to scale the normalized total to generate an energy value, and store the energy value in a register. System software may then read the energy value from the register and determine an energy usage for at least one application dependent upon the energy value.

Abstract translation: 公开了可以监测能量使用的计算系统的实施例。 这些实施例可以提供用于确定给定应用或过程的能量使用的低开销方法。 电路被配置为为多个操作中的每一个确定相应的能量，并对多个操作中的至少一些操作求和各个能量以产生归一化总计。 电路还可以被配置为缩放归一化总计以产生能量值，并将能量值存储在寄存器中。 然后，系统软件可以从寄存器读取能量值，并根据能量值确定至少一个应用的能量使用。

公开(公告)号：US20200319690A1

公开(公告)日：2020-10-08

申请号：US16373461

申请日：2019-04-02

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Daniel U. Becker ,  Achmed R. Zahir

IPC: G06F1/3206 ,  G06F1/3234

Abstract: An apparatus includes a processing circuit, a power processing module, and a power management circuit. The power management circuit is configured to estimate, over time, energy consumption of the processing circuit, and to sample the estimated energy consumption using a plurality of different sampling frequencies. Each of the different sampling frequencies is used to generate a respective set of power values. The power management circuit is further configured to track a particular characteristic for each set of power values, and then to provide, for each set of power values, a particular power value that corresponds to the particular characteristic to the power processing module. Based on at least one of the particular power values, the power processing module is configured to adjust an operating parameter of the processing circuit.