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1.发明授权Any size and location of concatenated packet data across SONET frames in a SONET signal 失效在SONET信号中SONET帧上连接的分组数据的任何大小和位置公开(公告)号：US06993047B1
公开(公告)日：2006-01-31
申请号：US09751764
申请日：2000-12-30
Applicant: Anurag Nigam , David Stiles
Inventor： Anurag Nigam , David Stiles
IPC: H04J3/24
CPC classification number: H04L45/00 , H04J3/1617 , H04J2203/0096
Abstract: Any size and location of concatenated packet data across Synchronous Optical Network (SONET) frames in a SONET signal is provided. In one embodiment, a method may include receiving portions of packets and placing the portions into buffers. Additionally, the method may determine packet boundaries among the portions of packets in the buffers to locate a number of packets. Additionally, the method may concatenate the packet data into a Time Division Multiplexing (TDM) SONET signal. The concatenation can be across any locations within the TDM SONET signal, and the size of the concatenation can be in increments of single SONET frames. In another embodiment, the number of packets may be concatenated within locations in the TDM SONET signal not occupied by the TDM data traffic. In one embodiment, the TDM SONET signal having the concatenated packet data may be transmitted.
Abstract translation: 提供了SONET信号中同步光网络（SONET）帧中连接分组数据的任何大小和位置。 在一个实施例中，方法可以包括接收分组的部分并将部分放置到缓冲器中。 此外，该方法可以确定缓冲器中的分组的部分之间的分组边界以定位多个分组。 此外，该方法可以将分组数据连接成时分复用（TDM）SONET信号。 级联可以在TDM SONET信号中的任何位置上，并且级联的大小可以是单个SONET帧的增量。 在另一个实施例中，分组数量可以被连接在未被TDM数据业务占用的TDM SONET信号中的位置内。 在一个实施例中，可以发送具有级联分组数据的TDM SONET信号。
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2.发明授权Any size and location of concatenated packet data across SONET frames in a SONET signal 有权在SONET信号中SONET帧上连接的分组数据的任何大小和位置公开(公告)号：US07272157B2
公开(公告)日：2007-09-18
申请号：US11036224
申请日：2005-01-14
Applicant: Anurag Nigam , David Stiles
Inventor： Anurag Nigam , David Stiles
IPC: H04J3/24
CPC classification number: H04L45/00 , H04J3/1617 , H04J2203/0096
Abstract: A method and apparatus for the incorporation of any size and location of concatenated SONET frames, which carry packet data, in an SONET signal are described. In an embodiment, a method includes receiving packet data. Additionally, the method includes concatenating the packet data into a Time Division Multiplexing (TDM) Synchronous Optical Network (SONET) signal. The concatenation can be across any locations within the TDM SONET signal, and a size of the concatenation can be in increments of single SONET frames. The method also includes transmitting the TDM SONET signal having the concatenated packet data.
Abstract translation: 描述了一种用于将携带分组数据的级联SONET帧的任何大小和位置并入SONET信号中的方法和装置。 在一个实施例中，一种方法包括接收分组数据。 另外，该方法包括将分组数据连接成时分复用（TDM）同步光网络（SONET）信号。 级联可以在TDM SONET信号中的任何位置上，并且级联的大小可以是单个SONET帧的增量。 该方法还包括发送具有级联分组数据的TDM SONET信号。
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公开(公告)号：US20050122969A1
公开(公告)日：2005-06-09
申请号：US11036224
申请日：2005-01-14
Applicant: Anurag Nigam , David Stiles
Inventor： Anurag Nigam , David Stiles
CPC classification number: H04L45/00 , H04J3/1617 , H04J2203/0096
Abstract: A method and apparatus for the incorporation of any size and location of concatenated SONET frames, which carry packet data, in an SONET signal are described. In an embodiment, a method includes receiving packet data. Additionally, the method includes concatenating the packet data into a Time Division Multiplexing (TDM) Synchronous Optical Network (SONET) signal. The concatenation can be across any locations within the TDM SONET signal, and a size of the concatenation can be in increments of single SONET frames. The method also includes transmitting the TDM SONET signal having the concatenated packet data.
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4.发明授权Any size and location of concatenated packet data across SONET frames in a SONET signal 失效在SONET信号中SONET帧上连接的分组数据的任何大小和位置公开(公告)号：US07460554B2
公开(公告)日：2008-12-02
申请号：US11035639
申请日：2005-01-14
Applicant: Anurag Nigam , David Stiles
Inventor： Anurag Nigam , David Stiles
IPC: H04L12/28
CPC classification number: H04L45/00 , H04J3/1617 , H04J2203/0096
Abstract: A method and apparatus for the incorporation of any size and location of concatenated SONET frames, which carry packet data, in an SONET signal are described. In an embodiment, a method includes receiving packet data. Additionally, the method includes concatenating the packet data into a Time Division Multiplexing (TDM) Synchronous Optical Network (SONET) signal. The concatenation can be across any locations within the TDM SONET signal, and a size of the concatenation can be in increments of single SONET frames. The method also includes transmitting the TDM SONET signal having the concatenated packet data.
Abstract translation: 描述了一种用于将携带分组数据的级联SONET帧的任何大小和位置并入SONET信号中的方法和装置。 在一个实施例中，一种方法包括接收分组数据。 另外，该方法包括将分组数据连接成时分复用（TDM）同步光网络（SONET）信号。 级联可以在TDM SONET信号中的任何位置上，并且级联的大小可以是单个SONET帧的增量。 该方法还包括发送具有级联分组数据的TDM SONET信号。
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5.发明申请Any size and location of concatenated packet data across SONET frames in a SONET signal 失效在SONET信号中SONET帧上连接的分组数据的任何大小和位置公开(公告)号：US20050135436A1
公开(公告)日：2005-06-23
申请号：US11035639
申请日：2005-01-14
Applicant: Anurag Nigam , David Stiles
Inventor： Anurag Nigam , David Stiles
CPC classification number: H04L45/00 , H04J3/1617 , H04J2203/0096
Abstract: A method and apparatus for the incorporation of any size and location of concatenated SONET frames, which carry packet data, in an SONET signal are described. In an embodiment, a method includes receiving packet data. Additionally, the method includes concatenating the packet data into a Time Division Multiplexing (TDM) Synchronous Optical Network (SONET) signal. The concatenation can be across any locations within the TDM SONET signal, and a size of the concatenation can be in increments of single SONET frames. The method also includes transmitting the TDM SONET signal having the concatenated packet data.
Abstract translation: 描述了一种用于将携带分组数据的级联SONET帧的任何大小和位置并入SONET信号中的方法和装置。 在一个实施例中，一种方法包括接收分组数据。 另外，该方法包括将分组数据连接成时分复用（TDM）同步光网络（SONET）信号。 级联可以在TDM SONET信号中的任何位置上，并且级联的大小可以是单个SONET帧的增量。 该方法还包括发送具有级联分组数据的TDM SONET信号。
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Patent Agency Ranking
6.发明授权System and method for characterizing a signal path using a sub-chip sampler 有权使用子芯片采样器来表征信号路径的系统和方法公开(公告)号：US07165200B2
公开(公告)日：2007-01-16
申请号：US11124458
申请日：2005-05-05
Applicant: Nilay D. Jani , Anurag Nigam , Cynthia M. Furse
Inventor： Nilay D. Jani , Anurag Nigam , Cynthia M. Furse
IPC: G01R31/28
CPC classification number: G01R31/088 , G01R31/007 , G01R31/024 , G01R31/11
Abstract: A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency. The system further includes a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal. A sub-chip sampler is configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency of the system clock signal.
Abstract translation: 公开了用于表征信号路径的系统和方法。 该系统包括被配置为以采样频率产生系统时钟信号的系统时钟。 分频器被配置为将系统时钟信号的采样频率除以因子N以产生芯片频率的芯片时钟信号。 所述系统还包括伪噪声（PN）序列发生器，其被配置为产生芯片频率的PN序列，并且在信号路径携带操作信号时将PN序列耦合到信号路径。 子芯片采样器被配置为使PN序列和已经在信号路径中反射的反射PN序列相关联，以形成相关信号并且以系统时钟信号的采样频率对相关信号进行采样。
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公开(公告)号：US06349092B1
公开(公告)日：2002-02-19
申请号：US09192975
申请日：1998-11-16
Applicant: Patrick R. Bisson , Paul M. Elliott , Kate B. Amon , Anurag Nigam , Phu S. Le
Inventor： Patrick R. Bisson , Paul M. Elliott , Kate B. Amon , Anurag Nigam , Phu S. Le
IPC: H04L1228
CPC classification number: H04J3/085 , H04J2203/0042 , H04J2203/0051 , H04J2203/006
Abstract: The present invention provides a method and structure for allowing more than 16 nodes to be configured in a single SONET BLSR network by utilizing unused portions of the transport overhead of an STS-N frame to expand the node identification field from 4 bits to 8 bits, thereby allowing up to 256 nodes to be present on a single ring.
Abstract translation: 本发明提供一种方法和结构，用于通过利用STS-N帧的传输开销的未使用部分，将单个SONET BLSR网络中的16个节点配置为将节点识别字段从4位扩展到8位， 从而允许在单个环上存在多达256个节点。
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8.发明授权Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous payload envelopes in synchronous optical networks 有权基于板载RAM的FIFO，指向同步光网络中同步有效负载信封的缓冲开销字节公开(公告)号：US07277447B2
公开(公告)日：2007-10-02
申请号：US09823293
申请日：2001-03-30
Applicant: James Wang , Anurag Nigam , David R. Stiles
Inventor： James Wang , Anurag Nigam , David R. Stiles
IPC: H04L12/56
CPC classification number: H04J3/0623 , H04J2203/0089
Abstract: An on-chip RAM FIFO (first-in-first-out) buffer for storing SPE overhead bytes wherein each entry of the RAM FIFO stores (1) a byte of the SPE overhead; (2) an indication of which byte of the SPE overhead is currently stored in that entry; and (3) an indication of which STS signal that byte was taken from.
Abstract translation: 用于存储SPE开销字节的片上RAM FIFO（先进先出）缓冲器，其中RAM FIFO的每个条目存储（1）SPE开销的字节; （2）当前存储在该条目中的SPE开销的哪个字节的指示; 和（3）从哪个字节获取哪个STS信号的指示。
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9.发明申请System and method for characterizing a signal path using a sub-chip sampler 有权使用子芯片采样器来表征信号路径的系统和方法公开(公告)号：US20050289408A1
公开(公告)日：2005-12-29
申请号：US11124458
申请日：2005-05-05
Applicant: Nilay Jani , Anurag Nigam , Cynthia Furse
Inventor： Nilay Jani , Anurag Nigam , Cynthia Furse
CPC classification number: G01R31/088 , G01R31/007 , G01R31/024 , G01R31/11
Abstract: A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency. The system further includes a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal. A sub-chip sampler is configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency of the system clock signal.
Abstract translation: 公开了用于表征信号路径的系统和方法。 该系统包括被配置为以采样频率产生系统时钟信号的系统时钟。 分频器被配置为将系统时钟信号的采样频率除以因子N以产生芯片频率的芯片时钟信号。 所述系统还包括伪噪声（PN）序列发生器，其被配置为产生芯片频率的PN序列，并且在信号路径携带操作信号时将PN序列耦合到信号路径。 子芯片采样器被配置为使PN序列和已经在信号路径中反射的反射PN序列相关联，以形成相关信号并且以系统时钟信号的采样频率对相关信号进行采样。
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公开(公告)号：US6012133A
公开(公告)日：2000-01-04
申请号：US969011
申请日：1997-11-12
Applicant: H. Victor Shadan , Anurag Nigam
Inventor： H. Victor Shadan , Anurag Nigam
CPC classification number: G11C15/00 , G06F12/1027
Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.
Abstract translation: 一种用于将具有多个匹配线的内容可寻址存储器（CAM）的逻辑值传送到具有多个字线的随机存取存储器（RAM）的电路。 第一逻辑门具有耦合到多个匹配线中的第一匹配线的输入，并且第二逻辑门具有耦合到多个匹配线中的第二匹配线的输入。 第一开关耦合在第一逻辑门的输出和第一字线之间，第二开关耦合在第二逻辑门的输出和第二字线之间。 第一开关由第二逻辑门的输出控制，使得当第二匹配线具有第二逻辑值时第一开关被打开，并且当第二匹配线具有第一逻辑值时闭合。 第二开关由第一逻辑门的输出控制，使得当第一匹配线具有第二逻辑值时第二开关打开，并且当第一匹配线具有第一逻辑值时闭合。
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