公开(公告)号：US6012133A

公开(公告)日：2000-01-04

申请号：US969011

申请日：1997-11-12

Applicant: H. Victor Shadan ,  Anurag Nigam

Inventor： H. Victor Shadan ,  Anurag Nigam

IPC: G06F12/10 ,  G11C15/00 ,  G06F12/08

CPC classification number: G11C15/00 ,  G06F12/1027

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.

Abstract translation: 一种用于将具有多个匹配线的内容可寻址存储器（CAM）的逻辑值传送到具有多个字线的随机存取存储器（RAM）的电路。 第一逻辑门具有耦合到多个匹配线中的第一匹配线的输入，并且第二逻辑门具有耦合到多个匹配线中的第二匹配线的输入。 第一开关耦合在第一逻辑门的输出和第一字线之间，第二开关耦合在第二逻辑门的​​输出和第二字线之间。 第一开关由第二逻辑门的​​输出控制，使得当第二匹配线具有第二逻辑值时第一开关被打开，并且当第二匹配线具有第一逻辑值时闭合。 第二开关由第一逻辑门的输出控制，使得当第一匹配线具有第二逻辑值时第二开关打开，并且当第一匹配线具有第一逻辑值时闭合。

公开(公告)号：US5893929A

公开(公告)日：1999-04-13

申请号：US639555

申请日：1996-04-29

Applicant: H. Victor Shadan ,  Anurag Nigam

Inventor： H. Victor Shadan ,  Anurag Nigam

IPC: G06F12/10 ,  G11C15/00 ,  G06F12/08

CPC classification number: G11C15/00 ,  G06F12/1027

Abstract: A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate has an input coupled to a second match line of the plurality of match lines. A first switch is coupled between an output of the first logic gate and a first word line, and a second switch is coupled between an output of the second logic gate and a second word line. The first switch is controlled by the output of the second logic gate such that the first switch is opened when the second match line has a second logic value and closed when the second match line has a first logic value. The second switch is controlled by the output of the first logic gate such that the second switch is opened when the first match line has the second logic value and closed when the first match line has the first logic value.