公开(公告)号：US12267058B1

公开(公告)日：2025-04-01

申请号：US17942093

申请日：2022-09-09

Applicant: Ambarella International LP

Inventor： Yueh Chun Cheng

IPC: G05F3/26 ,  H03H7/01

Abstract: An adaptive-bias metal-oxide-semiconductor (MOS) device comprises a first terminal, a second terminal, a third terminal, a first MOS device, and a second MOS device. The first MOS device generally may have a first width and a first gate length. The second MOS device generally may have a second width and a second gate length. The first terminal may be connected to a first source terminal of the first MOS device and a second source terminal of the second MOS device. The second terminal may be connected to a first drain terminal of the first MOS device, a first gate terminal of the first MOS device, and a second gate terminal of the second MOS device. The third terminal may be connected to a second drain terminal of the second MOS device. The first MOS device and the second MOS device are generally configured to operate in a sub-threshold operating region.

公开(公告)号：US11791828B1

公开(公告)日：2023-10-17

申请号：US17948910

申请日：2022-09-20

Applicant: Ambarella International LP

Inventor： Yueh Chun Cheng

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03B5/12

CPC classification number: H03L7/0891 ,  H03B5/1228 ,  H03L7/093 ,  H03L7/0992

Abstract: An apparatus comprises a cross-coupled differential amplifier, an inductive-capacitive (LC) tank circuit, and a low-noise voltage supply. The inductive-capacitive (LC) tank circuit is generally coupled in a feedback path of the cross-coupled differential amplifier. The LC tank circuit generally comprises (i) an inductance provided by an inductor, (ii) a first capacitance provided by a parallel coupled varactor circuit, (iii) a second capacitance provided by a parallel coupled first switched-capacitor bank, and (iv) a third capacitance provided by a parallel coupled second switched-capacitor bank. The low-noise voltage supply may be configured to provide a supply voltage of the cross-coupled differential amplifier. The parallel coupled varactor circuit comprises a pair of thick oxide varactors connected with a reverse varactor connection. The parallel coupled first switched-capacitor bank and the parallel coupled second switched-capacitor bank comprise thin oxide switches.

公开(公告)号：US11705895B1

公开(公告)日：2023-07-18

申请号：US17834897

申请日：2022-06-07

Applicant: Ambarella International LP

Inventor： Yueh Chun Cheng

IPC: H03K5/1252 ,  G05F1/56 ,  H03K3/03 ,  H03K3/011 ,  H03L1/00

CPC classification number: H03K5/1252 ,  G05F1/56 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/0322 ,  H03L1/00

Abstract: An apparatus comprises a first circuit, a second circuit, a first transistor, a second transistor, a third transistor, a first programmable resistance, and a second programmable resistance. The first circuit may be configured to generate a reference signal and a bias signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit may be connected to the first circuit and a ring oscillator. The first transistor may be connected to the first circuit and configured to set a first reference current of the first circuit based on the first input signal and the first programmable resistance. The second transistor may be connected in parallel with the first transistor. The second transistor is generally diode-connected. The third transistor may be connected to the first circuit and configured to set a second reference current of the first circuit based on the first input signal and the second programmable resistance. The first circuit generally forms a current mirror with the second circuit. The second circuit may be configured to provide a programmable current ratio for the current mirror based on a value of a second input signal.

公开(公告)号：US11870450B1

公开(公告)日：2024-01-09

申请号：US17683613

申请日：2022-03-01

Applicant: Ambarella International LP

Inventor： Yueh Chun Cheng ,  Xuan Wang

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/089

CPC classification number: H03L7/0992 ,  H03L7/0893 ,  H03L7/0995 ,  H03L2207/06

Abstract: An apparatus comprises a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first frequency in response to a voltage level of a first input signal and a value of a second input signal. The second circuit may be configured to determine the value of the second input signal based on a reference frequency signal, the first frequency of the output signal, a reference voltage, and a value representing a target frequency for the output signal.

公开(公告)号：US11843389B1

公开(公告)日：2023-12-12

申请号：US17892533

申请日：2022-08-22

Applicant: Ambarella International LP

Inventor： Yueh Chun Cheng

IPC: H03L7/099 ,  H03L7/08 ,  H03B5/04 ,  H03L7/089

CPC classification number: H03L7/0995 ,  H03B5/04 ,  H03L7/0802 ,  H03L7/0891

Abstract: An apparatus comprises a first circuit and a second circuit The first circuit may be configured to generate a control current signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit is generally connected to the first circuit and comprises a programmable ring oscillator configured to generate an output signal having a frequency based on the control current signal and a value of a second input signal.