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1.发明申请公开(公告)号：US20120046004A1
公开(公告)日：2012-02-23
申请号：US12806799
申请日：2010-08-19
CPC分类号： H03F3/45183 , H03F1/0277 , H03F3/189 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/336 , H03F2200/36 , H03F2200/39 , H03F2200/408 , H03F2200/429 , H03F2200/435 , H03F2200/498 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/45394 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45592 , H03F2203/45594 , H03F2203/45631 , H03F2203/45701 , H03F2203/45702 , H03F2203/45728 , H03G1/0088 , H03G3/3042
摘要： According to one embodiment, an improved preamplification chain for implementation in a transmitter comprises a frequency conversion stage for up-converting a baseband signal to a transmit signal, a variable gain control power amplifier driver for preamplifying the transmit signal, and a differential feedback calibration stage receiving first and second differential outputs of a current steering unit of the power amplifier driver and providing calibration feedback to a baseband signal generator of the transmitter. In one embodiment, the frequency conversion stage includes an adjustable low-pass filter for filtering the baseband signal, a passive mixer for up-converting the baseband signal to the transmit signal, and a clock conversion unit configured to convert a fifty percent (50%) duty cycle clock input to a twenty-five percent (25%) duty cycle clock output for driving the passive mixer.
摘要翻译： 根据一个实施例，用于在发射机中实现的改进的前置放大链包括用于将基带信号上变频到发射信号的变频级，用于对发射信号进行预放大的可变增益控制功率放大器驱动器和差分反馈校准级 接收功率放大器驱动器的电流转向单元的第一和第二差分输出，并向发射机的基带信号发生器提供校准反馈。 在一个实施例中，频率转换级包括用于对基带信号进行滤波的可调低通滤波器，用于将基带信号上变频为发射信号的无源混频器，以及时钟转换单元，被配置为将百分之五十（50％ ）占空比时钟输入到二十五％（25％）占空比时钟输出，用于驱动无源混频器。
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公开(公告)号：US08836374B2
公开(公告)日：2014-09-16
申请号：US13168143
申请日：2011-06-24
CPC分类号： H03K19/00 , H03F1/0261 , H03F3/189 , H03F3/245 , H03F3/45179 , H03F2200/27 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/555 , H03F2203/45394
摘要： According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.
摘要翻译： 根据一个实施例，用于通信系统的高性能缓冲器包括第一和第二差分块。 第一和第二差分块中的每一个包括用于产生用于高性能缓冲器的负载的驱动电流的一个或多个驱动晶体管，以及用于调整一个或多个驱动晶体管的操作的反馈路径。 反馈路径包括用于接收共模偏置电压的反馈晶体管，其中共模偏置电压至少部分地取决于反馈晶体管的阈值电压。 反馈路径包括可编程电阻器和电容器，以减少带外环路增益和噪声。 高性能缓冲器被配置为实现高线性度，低输出阻抗和低噪声，并且适合用作无线通信系统中的预混频器缓冲器。
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3.发明授权公开(公告)号：US08620242B2
公开(公告)日：2013-12-31
申请号：US12806799
申请日：2010-08-19
CPC分类号： H03F3/45183 , H03F1/0277 , H03F3/189 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/72 , H03F2200/336 , H03F2200/36 , H03F2200/39 , H03F2200/408 , H03F2200/429 , H03F2200/435 , H03F2200/498 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/45394 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45592 , H03F2203/45594 , H03F2203/45631 , H03F2203/45701 , H03F2203/45702 , H03F2203/45728 , H03G1/0088 , H03G3/3042
摘要： According to one embodiment, an improved preamplification chain for implementation in a transmitter comprises a frequency conversion stage for up-converting a baseband signal to a transmit signal, a variable gain control power amplifier driver for preamplifying the transmit signal, and a differential feedback calibration stage receiving first and second differential outputs of a current steering unit of the power amplifier driver and providing calibration feedback to a baseband signal generator of the transmitter. In one embodiment, the frequency conversion stage includes an adjustable low-pass filter for filtering the baseband signal, a passive mixer for up-converting the baseband signal to the transmit signal, and a clock conversion unit configured to convert a fifty percent (50%) duty cycle clock input to a twenty-five percent (25%) duty cycle clock output for driving the passive mixer.
摘要翻译： 根据一个实施例，用于在发射机中实现的改进的前置放大链包括用于将基带信号上变频到发射信号的变频级，用于对发射信号进行预放大的可变增益控制功率放大器驱动器和差分反馈校准级 接收功率放大器驱动器的电流转向单元的第一和第二差分输出，并向发射机的基带信号发生器提供校准反馈。 在一个实施例中，频率转换级包括用于对基带信号进行滤波的可调低通滤波器，用于将基带信号上变频为发射信号的无源混频器，以及时钟转换单元，被配置为将百分之五十（50％ ）占空比时钟输入到二十五％（25％）占空比时钟输出，用于驱动无源混频器。
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公开(公告)号：US20120326754A1
公开(公告)日：2012-12-27
申请号：US13168143
申请日：2011-06-24
IPC分类号： H03K3/00
CPC分类号： H03K19/00 , H03F1/0261 , H03F3/189 , H03F3/245 , H03F3/45179 , H03F2200/27 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/555 , H03F2203/45394
摘要： According to one embodiment, a high performance buffer for use in a communications system includes first and second differential blocks. Each of the first and second differential blocks comprise one or more driving transistors for generating a driving current for a load of the high performance buffer, and a feedback path for adjusting the operation of the one or more driving transistors. The feedback path includes a feedback transistor for receiving a common mode bias voltage, wherein the common mode bias voltage depends at least in part on a threshold voltage of the feedback transistor. The feedback path includes a programmable resistor and capacitor to reduce out of band loop gain and the noise. The high performance buffer is configured to achieve a high linearity, low output impedance, and low noise, and is suitable for use as a pre-mixer buffer in a wireless communications system.
摘要翻译： 根据一个实施例，用于通信系统的高性能缓冲器包括第一和第二差分块。 第一和第二差分块中的每一个包括用于产生用于高性能缓冲器的负载的驱动电流的一个或多个驱动晶体管，以及用于调整一个或多个驱动晶体管的操作的反馈路径。 反馈路径包括用于接收共模偏置电压的反馈晶体管，其中共模偏置电压至少部分地取决于反馈晶体管的阈值电压。 反馈路径包括可编程电阻器和电容器，以减少带外环路增益和噪声。 高性能缓冲器被配置为实现高线性度，低输出阻抗和低噪声，并且适合用作无线通信系统中的预混频器缓冲器。
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公开(公告)号：US07852147B1
公开(公告)日：2010-12-14
申请号：US12500306
申请日：2009-07-09
IPC分类号： H03K5/00
CPC分类号： H03H11/1291
摘要： An integrated circuit includes a signal-path filter, a high-pass filter, and a control circuit. The signal-path filter is configured to receive an input signal and provide an output signal. The high-pass filter is coupled to the signal-path filter and is configured to reduce a direct-current (DC) component of the input signal. The high-pass filter includes a metal-oxide-semiconductor (MOS) switch, wherein a corner frequency of the high-pass filter is based on a resistance of the MOS switch. The control circuit is configured to provide a control voltage to the MOS switch. The control circuit includes a reference resistor, wherein the resistance of the MOS switch substantially tracks the resistance of the reference resistor. The integrated circuit may be embodied in software and/or included in a device (e.g., a mobile telephone) that receives and filters a signal.
摘要翻译： 集成电路包括信号路径滤波器，高通滤波器和控制电路。 信号路径滤波器被配置为接收输入信号并提供输出信号。 高通滤波器耦合到信号路径滤波器，并且被配置为减小输入信号的直流（DC）分量。 高通滤波器包括金属氧化物半导体（MOS）开关，其中高通滤波器的转角频率基于MOS开关的电阻。 控制电路被配置为向MOS开关提供控制电压。 控制电路包括参考电阻器，其中MOS开关的电阻基本上跟踪参考电阻器的电阻。 集成电路可以以软件和/或包含在接收和过滤信号的设备（例如，移动电话）中来实现。
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公开(公告)号：US08446229B2
公开(公告)日：2013-05-21
申请号：US12546397
申请日：2009-08-24
CPC分类号： H03J5/24 , H03J2200/10
摘要： Embodiments of a capacitive tuning system implementing a tunable capacitive array are presented herein. The tunable capacitive array includes both scaled coarse capacitors and one or more fine capacitors. The one or more fine capacitors advantageously reduce a differential nonlinearity associated with the scaled coarse capacitors. The use of fine capacitors limits additional area requirements in an integrated circuit implementation, while improving the accuracy of the capacitive tuning system.
摘要翻译： 本文给出了实现可调谐电容阵列的电容调谐系统的实施例。 可调电容阵列包括缩放粗略电容器和一个或多个精细电容器。 一个或多个精细电容器有利地降低与缩放的粗糙电容器相关联的差分非线性。 精细电容器的使用在集成电路实现中限制了额外的面积要求，同时提高了电容调谐系统的精度。
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公开(公告)号：US20110025436A1
公开(公告)日：2011-02-03
申请号：US12546397
申请日：2009-08-24
IPC分类号： H03J5/24
CPC分类号： H03J5/24 , H03J2200/10
摘要： Embodiments of a capacitive tuning system implementing a tunable capacitive array are presented herein. The tunable capacitive array includes both scaled coarse capacitors and one or more fine capacitors. The one or more fine capacitors advantageously reduce a differential nonlinearity associated with the scaled coarse capacitors. The use of fine capacitors limits additional area requirements in an integrated circuit implementation, while improving the accuracy of the capacitive tuning system.
摘要翻译： 本文给出了实现可调谐电容阵列的电容调谐系统的实施例。 可调电容阵列包括缩放粗略电容器和一个或多个精细电容器。 一个或多个精细电容器有利地降低与缩放的粗糙电容器相关联的差分非线性。 精细电容器的使用在集成电路实现中限制了额外的面积要求，同时提高了电容调谐系统的精度。
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8.发明授权Compact low-power receiver including transimpedance amplifier, digitally controlled interface circuit, and low pass filter 有权紧凑型低功率接收器，包括跨阻放大器，数字控制接口电路和低通滤波器公开(公告)号：US08452253B2
公开(公告)日：2013-05-28
申请号：US12804397
申请日：2010-07-20
IPC分类号： H04B1/10
CPC分类号： H03H11/1217 , H03F1/0205 , H03F1/086 , H03F3/19 , H03F3/45076 , H03F2200/294 , H03F2200/451 , H03F2200/91 , H03F2203/45332 , H03F2203/45336 , H03G1/0005 , H03G1/0029 , H03G3/3068 , H03G3/32 , H03H11/1252 , H03H11/1256 , H03H11/1291 , H03H2210/025 , H04B1/123 , H04B1/16 , H04L25/06
摘要： According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.
摘要翻译： 根据一个实施例，紧凑型低功率接收机包括由数字控制接口电路连接的第一和第二模拟电路。 第一模拟电路在输出处具有第一直流（DC）偏移和第一共模电压，并且第二模拟电路在输入端具有第二直流偏移和第二共模电压。 数字控制接口电路将输出连接到输入，并且被配置为匹配第一和第二DC偏移并且匹配第一和第二共模电压。 在一个实施例中，第一模拟电路是使用电流模式缓冲器实现的可变增益控制跨阻抗放大器（TIA），第二模拟电路是二阶可调低通滤波器，由此三极可调低通滤波器 在紧凑型低功率接收机中有效生产。
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9.发明申请Compact low-power receiver including transimpedance amplifier, digitally controlled interface circuit, and low pass filter 有权紧凑型低功率接收器，包括跨阻放大器，数字控制接口电路和低通滤波器公开(公告)号：US20120021712A1
公开(公告)日：2012-01-26
申请号：US12804397
申请日：2010-07-20
IPC分类号： H04B7/00
CPC分类号： H03H11/1217 , H03F1/0205 , H03F1/086 , H03F3/19 , H03F3/45076 , H03F2200/294 , H03F2200/451 , H03F2200/91 , H03F2203/45332 , H03F2203/45336 , H03G1/0005 , H03G1/0029 , H03G3/3068 , H03G3/32 , H03H11/1252 , H03H11/1256 , H03H11/1291 , H03H2210/025 , H04B1/123 , H04B1/16 , H04L25/06
摘要： According to one embodiment, a compact low-power receiver comprises first and second analog circuits connected by a digitally controlled interface circuit. The first analog circuit has a first direct-current (DC) offset and a first common mode voltage at an output, and the second analog circuit has a second DC offset and a second common mode voltage at an input. The digitally controlled interface circuit connects the output to the input, and is configured to match the first and second DC offsets and to match the first and second common mode voltages. In one embodiment, the first analog circuit is a variable gain control transimpedance amplifier (TIA) implemented using a current mode buffer, the second analog circuit is a second-order adjustable low-pass filter, whereby a three-pole adjustable low-pass filter in the compact low-power receiver is effectively produced.
摘要翻译： 根据一个实施例，紧凑型低功率接收机包括由数字控制接口电路连接的第一和第二模拟电路。 第一模拟电路在输出处具有第一直流（DC）偏移和第一共模电压，并且第二模拟电路在输入端具有第二直流偏移和第二共模电压。 数字控制接口电路将输出连接到输入，并且被配置为匹配第一和第二DC偏移并且匹配第一和第二共模电压。 在一个实施例中，第一模拟电路是使用电流模式缓冲器实现的可变增益控制跨阻抗放大器（TIA），第二模拟电路是二阶可调低通滤波器，由此三极可调低通滤波器 在紧凑型低功率接收机中有效生产。
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