公开(公告)号：US20170315915A1

公开(公告)日：2017-11-02

申请号：US15143032

申请日：2016-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh Meswani

IPC: G06F12/0808 ,  G06F12/0811

CPC classification number: G06F9/5016 ,  Y02D10/22

Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.

公开(公告)号：US09443561B1

公开(公告)日：2016-09-13

申请号：US14719200

申请日：2015-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David Roberts ,  Yasuko Eckert ,  Mitesh Meswani ,  Indrani Paul

IPC: G11C5/02 ,  H04L12/933 ,  G06F13/42 ,  G11C5/06 ,  G06F13/40

CPC classification number: G11C5/02 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/42 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  Y02D10/14 ,  Y02D10/151

Abstract: Embodiments are described for a communications interconnect scheme for 3D stacked memory devices. A ring network design is used for networks of memory chips organized as individual devices with multiple dies or wafers. The design comprises a three-tier ring network where each ring serves a different set of memory blocks. One ring or set of rings interconnects memory within a die (inter-bank), a second ring or set of rings interconnects memory across die in a stack (inter-die), and the third ring or set of rings interconnects memory across stacks or chip packages (inter-stack).

Abstract translation: 针对3D堆叠存储器件的通信互连方案描述了实施例。 环形网络设计用于组织为具有多个管芯或晶片的单独器件的存储器芯片的网络。 该设计包括三层环网，其中每个环服务不同的存储块集合。 一个环或一组环将管芯内的存储器互相互连（第二环或一组环）在堆叠（管芯间）中跨芯片互连存储器，并且第三环或一组环将堆叠互连存储器 芯片封装（堆叠）。

公开(公告)号：US09377954B2

公开(公告)日：2016-06-28

申请号：US14273751

申请日：2014-05-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh ,  Mitesh Meswani ,  Michael Ignatowski ,  Mark Nutter

IPC: H01L29/00 ,  G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0685 ,  G06F12/023 ,  G06F2212/205 ,  Y02D10/13

Abstract: A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

Abstract translation: 用于多类存储器系统中的存储器分配的系统包括可耦合到共享统一存储器地址空间的多个存储器的处理器和用于存储软件功能库的库存储。 处理器响应于对库的存储器分配功能调用来分配存储器到数据结构来识别数据结构的类型。 使用库，处理器基于数据结构的类型在多类存储器系统的多个存储器之间分配数据结构的一部分。

公开(公告)号：US10324760B2

公开(公告)日：2019-06-18

申请号：US15143032

申请日：2016-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh Meswani

IPC: G06F12/08 ,  G06F9/50

Abstract: The described embodiments include a computing device that has two or more levels of memory, each level of memory having different performance characteristics. During operation, the computing device receives a request to lease an available block of memory in a specified level of memory for storing an object. When a block of memory is available for leasing in the specified level of memory, the computing device stores the object in the block of memory in the specified level of memory. The computing device also commences the lease for the block of memory by setting an indicator for the block of memory to indicate that the block of memory is leased. During the lease (i.e., until the lease is terminated), the object is kept in the block of memory.

公开(公告)号：US20150324131A1

公开(公告)日：2015-11-12

申请号：US14273751

申请日：2014-05-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh ,  Mitesh Meswani ,  Michael Ignatowski ,  Mark Nutter

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0685 ,  G06F12/023 ,  G06F2212/205 ,  Y02D10/13

Abstract: A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

Abstract translation: 用于多类存储器系统中的存储器分配的系统包括可耦合到共享统一存储器地址空间的多个存储器的处理器和用于存储软件功能库的库存储。 处理器响应于对库的存储器分配功能调用来分配存储器到数据结构来识别数据结构的类型。 使用库，处理器基于数据结构的类型在多类存储器系统的多个存储器之间分配数据结构的一部分。

公开(公告)号：US20150206574A1

公开(公告)日：2015-07-23

申请号：US14160618

申请日：2014-01-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Joseph L. Greathouse ,  Ciji Isen ,  Mitesh Meswani

IPC: G11C11/406 ,  G11C14/00

CPC classification number: G11C14/0018 ,  G06F13/1636 ,  G11C11/406 ,  Y02D10/14

Abstract: A method includes emptying a first region of a dynamic random access memory of data by moving data from the first region to a non-volatile memory and reducing a refresh rate of the dynamic random access memory responsive to emptying the first region of data. A system includes a memory controller to refresh a dynamic random access memory based on a configurable refresh rate, the dynamic random access memory having a plurality of regions, each region having an associated minimum refresh rate, and a processing unit to empty a first region of the plurality of regions of the dynamic random access memory by moving data from the first region to a non-volatile memory and to reduce the configurable refresh rate responsive to emptying the first region.

Abstract translation: 一种方法包括通过将数据从第一区域移动到非易失性存储器来清空数据的动态随机存取存储器的第一区域，并且响应于排空第一数据区域而减小动态随机存取存储器的刷新率。 一种系统包括：存储器控制器，用于基于可配置刷新速率来刷新动态随机存取存储器，所述动态随机存取存储器具有多个区域，每个区域具有相关联的最小刷新率;以及处理单元， 动态随机存取存储器的多个区域通过将数据从第一区域移动到非易失性存储器并且响应于排空第一区域而减小可配置的刷新率。